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h c 05 mc68hc05b6/d rev. 3 mc68hc05b4 mc68hc705b5 mc68hc05b6 mc68hc05b8 mc68hc05b16 mc68hc705b16 mc68hc05b32 mc68hc705b32 technical data mc68hc05b6 !motorola technical data

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information appendices high speed operation
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information mc68hc05b4 high speed operation
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 all products are sold on motorolas terms & conditions of supply. in ordering a product covered by this document the customer agrees to be bound by those terms & conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this notice). a copy of motorolas terms & conditions of supply is available on request. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters can and do vary in different applications. all operating parameters, including typicals, must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and ! are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. the customer should ensure that it has the most up to date version of the document by contacting its local motorola office. this document supersedes any earlier documentation relating to the products referred to herein. the information contained in this document is current at the date of publication. it may subsequently be updated, revised or withdrawn. ? motorola ltd., 1995 all t r ade mar ks recognised. this document contains inf or mation on ne w products . speci?cations and inf or mation herein are subject to change without notice . mc68hc05b6 high-density complementary metal oxide semiconductor (hcmos) microcomputer unit
2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 caution this document includes descriptions of the various self-check and bootstrap mechanisms that are currently implemented as firmware in the non-user rom areas of the mc68hc05b6 and related devices. as these firmware routines are intended primarily to help motorolas engineers test the devices, they may be changed or removed at any time. for this reason, motorola recommends that the self-check and bootstrap routines are not called from from the user software. customers who do call these routines from the user software do so at their own risk.
mc68hc05b6 motorola i table of contents paragraph number page number title 1 introduction 1.1 features................................................................................................................ 1-2 1.2 mask options for the mc68hc05b6 ..................................................................... 1-2 2 modes of operation and pin descriptions 2.1 modes of operation ............................................................................................... 2-1 2.1.1 single chip mode ............................................................................................ 2-1 2.1.2 self-check mode ............................................................................................. 2-1 2.2 serial ram loader ................................................................................................ 2-4 2.3 jump to any address........................................................................................... 2-4 2.4 low power modes................................................................................................. 2-7 2.4.1 stop .............................................................................................................. 2-7 2.4.2 wait ............................................................................................................... 2-9 2.4.2.1 power consumption during wait mode .................................................... 2-9 2.4.3 slow mode.................................................................................................... 2-10 2.4.3.1 miscellaneous register ............................................................................. 2-10 2.5 pin descriptions ................................................................................................... 2-11 2.5.1 vdd and vss ................................................................................................. 2-11 2.5.2 irq ................................................................................................................. 2-11 2.5.3 reset ............................................................................................................ 2-11 2.5.4 tcap1 ............................................................................................................ 2-11 2.5.5 tcap2 ............................................................................................................ 2-12 2.5.6 tcmp1............................................................................................................ 2-12 2.5.7 tcmp2............................................................................................................ 2-12 2.5.8 osc1, osc2 .................................................................................................. 2-12 2.5.8.1 crystal ....................................................................................................... 2-12 2.5.8.2 ceramic resonator..................................................................................... 2-12 2.5.8.3 external clock ............................................................................................ 2-13 2.5.9 rdi (receive data in)...................................................................................... 2-14 2.5.10 tdo (transmit data out).................................................................................. 2-14 2.5.11 sclk............................................................................................................... 2-14
motorola ii mc68hc05b6 table of contents (continued) paragraph number page number title 2.5.12 plma ...............................................................................................................2-14 2.5.13 plmb ...............................................................................................................2-14 2.5.14 vpp1................................................................................................................2-14 2.5.15 vrh .................................................................................................................2-14 2.5.16 vrl..................................................................................................................2-14 2.5.17 pa0 C pa7/pb0 C pb7/pc0 C pc7...................................................................2-14 2.5.18 pd0/an0Cpd7/an7 .........................................................................................2-14 3 memory and registers 3.1 registers ...............................................................................................................3-1 3.2 ram.......................................................................................................................3-1 3.3 rom ......................................................................................................................3-1 3.4 self-check rom ....................................................................................................3-2 3.5 eeprom ...............................................................................................................3-3 3.5.1 eeprom control register ................................................................................3-3 3.5.2 eeprom read operation .................................................................................3-5 3.5.3 eeprom erase operation ...............................................................................3-5 3.5.4 eeprom programming operation ...................................................................3-6 3.5.5 options register (optr) ..................................................................................3-6 3.6 eeprom during stop mode ...............................................................................3-7 3.7 eeprom during wait mode ................................................................................3-7 3.8 miscellaneous register .........................................................................................3-9 4 input/output ports 4.1 input/output programming .....................................................................................4-1 4.2 ports a and b ........................................................................................................4-2 4.3 port c ....................................................................................................................4-3 4.4 port d ....................................................................................................................4-3 4.5 port registers .........................................................................................................4-4 4.5.1 port data registers a and b (porta and portb) ..........................................4-4 4.5.2 port data register c (portc)..........................................................................4-4 4.5.3 port data register d (portd)..........................................................................4-5 4.5.3.1 a/d status/control register..........................................................................4-5 4.5.4 data direction registers (ddra, ddrb and ddrc)........................................4-5 4.6 other port considerations ......................................................................................4-6
mc68hc05b6 motorola iii table of contents (continued) paragraph number page number title 5 programmable timer 5.1 counter ................................................................................................................. 5-1 5.1.1 counter register and alternate counter register ............................................ 5-3 5.2 timer control and status ....................................................................................... 5-4 5.2.1 timer control register (tcr) ........................................................................... 5-4 5.2.2 timer status register (tsr)............................................................................. 5-6 5.3 input capture......................................................................................................... 5-7 5.3.1 input capture register 1 (icr1) ....................................................................... 5-7 5.3.2 input capture register 2 (icr2) ....................................................................... 5-8 5.4 output compare .................................................................................................... 5-9 5.4.1 output compare register 1 (ocr1) ................................................................. 5-9 5.4.2 output compare register 2 (ocr2) ................................................................. 5-10 5.4.3 software force compare .................................................................................. 5-11 5.5 pulse length modulation (plm) ........................................................................... 5-11 5.5.1 pulse length modulation registers a and b (plma/plmb) .......................... 5-11 5.6 timer during stop mode..................................................................................... 5-12 5.7 timer during wait mode...................................................................................... 5-12 5.8 timer state diagrams ............................................................................................ 5-12 6 serial communications interface 6.1 sci two-wire system features ............................................................................... 6-1 6.2 sci receiver features ............................................................................................ 6-3 6.3 sci transmitter features ........................................................................................ 6-3 6.4 functional description........................................................................................... 6-3 6.5 data format ........................................................................................................... 6-5 6.6 receiver wake-up operation ................................................................................. 6-5 6.6.1 idle line wake-up ............................................................................................. 6-6 6.6.2 address mark wake-up ................................................................................... 6-6 6.7 receive data in (rdi) ........................................................................................... 6-6 6.8 start bit detection.................................................................................................. 6-6 6.9 transmit data out (tdo) ....................................................................................... 6-8 6.10 sci synchronous transmission ............................................................................. 6-9 6.11 sci registers ......................................................................................................... 6-10 6.11.1 serial communications data register (scdr) ............................................... 6-10 6.11.2 serial communications control register 1 (sccr1) ...................................... 6-10 6.11.3 serial communications control register 2 (sccr2) ........................................ 6-14 6.11.4 serial communications status register (scsr) ............................................. 6-16
motorola iv mc68hc05b6 table of contents (continued) paragraph number page number title 6.11.5 baud rate register (baud) ...............................................................................6-18 6.12 baud rate selection................................................................................................6-19 6.13 sci during stop mode.........................................................................................6-21 6.14 sci during wait mode..........................................................................................6-21 7 pulse length d/a converters 7.1 miscellaneous register ..........................................................................................7-3 7.2 plm clock selection...............................................................................................7-4 7.3 plm during stop mode .......................................................................................7-4 7.4 plm during wait mode ........................................................................................7-4 8 analog to digital converter 8.1 a/d converter operation.........................................................................................8-1 8.2 a/d registers..........................................................................................................8-3 8.2.1 port d data register (portd)..........................................................................8-3 8.2.2 a/d result data register (addata) ...................................................................8-3 8.2.3 a/d status/control register (adstat)...............................................................8-4 8.3 a/d converter during stop mode.........................................................................8-5 8.4 a/d converter during wait mode..........................................................................8-6 8.5 port d analog input................................................................................................8-6 9 resets and interrupts 9.1 resets ...................................................................................................................9-1 9.1.1 power-on reset.................................................................................................9-2 9.1.2 miscellaneous register ...................................................................................9-2 9.1.3 reset pin .......................................................................................................9-3 9.1.4 computer operating properly (cop) watchdog reset.......................................9-3 9.1.4.1 cop watchdog during stop mode ...........................................................9-4 9.1.4.2 cop watchdog during wait mode ............................................................9-4 9.1.5 functions affected by reset..............................................................................9-5 9.2 interrupts ...............................................................................................................9-6 9.2.1 interrupt priorities.............................................................................................9-6 9.2.2 nonmaskable software interrupt (swi) ............................................................9-6 9.2.3 maskable hardware interrupts..........................................................................9-7
mc68hc05b6 motorola v table of contents (continued) paragraph number page number title 9.2.3.1 external interrupt ( irq) ............................................................................. 9-7 9.2.3.2 miscellaneous register ............................................................................. 9-9 9.2.3.3 timer interrupts ......................................................................................... 9-10 9.2.3.4 serial communications interface (sci) interrupts ...................................... 9-10 9.2.4 hardware controlled interrupt sequence ......................................................... 9-11 10 cpu core and instruction set 10.1 registers............................................................................................................. 10-1 10.1.1 accumulator (a) ............................................................................................ 10-2 10.1.2 index register (x)........................................................................................... 10-2 10.1.3 program counter (pc) ................................................................................... 10-2 10.1.4 stack pointer (sp) ......................................................................................... 10-2 10.1.5 condition code register (ccr) ...................................................................... 10-2 10.2 instruction set ..................................................................................................... 10-3 10.2.1 register/memory instructions ....................................................................... 10-4 10.2.2 branch instructions ....................................................................................... 10-4 10.2.3 bit manipulation instructions ......................................................................... 10-4 10.2.4 read/modify/write instructions ...................................................................... 10-4 10.2.5 control instructions ....................................................................................... 10-4 10.2.6 tables............................................................................................................ 10-4 10.3 addressing modes .............................................................................................. 10-11 10.3.1 inherent......................................................................................................... 10-11 10.3.2 immediate ..................................................................................................... 10-11 10.3.3 direct............................................................................................................. 10-11 10.3.4 extended....................................................................................................... 10-12 10.3.5 indexed, no offset.......................................................................................... 10-12 10.3.6 indexed, 8-bit offset....................................................................................... 10-12 10.3.7 indexed, 16-bit offset..................................................................................... 10-12 10.3.8 relative ......................................................................................................... 10-13 10.3.9 bit set/clear ................................................................................................... 10-13 10.3.10 bit test and branch ........................................................................................ 10-13
motorola vi mc68hc05b6 table of contents (continued) paragraph number page number title 11 electrical specifications 11.1 maximum ratings ................................................................................................11-1 11.2 thermal characteristics and power considerations .............................................11-2 11.3 dc electrical characteristics ..............................................................................11-3 11.3.1 i dd trends for 5v operation ...............................................................11-4 11.3.2 i dd trends for 3.3v operation ..............................................................11-7 11.4 a/d converter characteristics ...........................................................................11-9 11.5 control timing ..............................................................................................11-11 12 mechanical data 12.1 mc68hc05b6 pin con?gurations ........................................................................12-1 12.1.1 52-pin plastic leaded chip carrier (plcc) .....................................................12-1 12.1.2 64-pin quad ?at pack (qfp) ..........................................................................12-2 12.1.3 56-pin shrink dual in line package (sdip) ....................................................12-3 12.2 mc68hc05b6 mechanical dimensions ...............................................................12-4 12.2.1 52-pin plastic leaded chip carrier (plcc) .....................................................12-4 12.2.2 64-pin quad ?at pack (qfp) .........................................................................12-5 12.2.3 56-pin shrink dual in line package (sdip)......................................................12-6 13 ordering information 13.1 eproms .............................................................................................................13-2 13.2 veri?cation media ................................................................................................13-2 13.3 rom veri?cation units (rvu)...............................................................................13-2
mc68hc05b6 motorola vii table of contents (continued) paragraph number page number title a mc68hc05b4 b mc68hc05b8 c mc68hc705b5 c.1 eprom.................................................................................................................c-5 c.1.1 eprom programming operation.....................................................................c-5 c.2 eprom registers..................................................................................................c-6 c.2.1 eprom control register ...............................................................................c-6 c.3 options register (optr) ......................................................................................c-7 c.4 bootstrap mode ....................................................................................................c-8 c.4.1 erased eprom veri?cation ............................................................................c-11 c.4.2 eprom parallel bootstrap load.......................................................................c-11 c.4.3 eprom (ram) serial bootstrap load and execute..........................................c-13 c.4.4 ram parallel bootstrap load and execute .......................................................c-14 c.4.5 bootstrap loader timing diagrams ............................................................c-17 c.5 dc electrical characteristics .................................................................................c-19 c.6 control timing........................................................................................................c-19 d mc68hc05b16 d.1 self-check routines ..............................................................................................d-1 e mc68hc705b16 e.1 eprom................................................................................................................. e-5 e.1.1 eprom read operation................................................................................... e-5 e.1.2 eprom program operation............................................................................. e-5 e.1.3 eprom/eeprom/eclk control register ..................................................... e-6 e.1.4 mask option register ...................................................................................... e-8 e.1.5 eeprom options register (optr) ................................................................ e-9 e.2 bootstrap mode .................................................................................................... e-10 e.2.1 erased eprom veri?cation ............................................................................ e-13
motorola viii mc68hc05b6 table of contents (continued) paragraph number page number title e.2.2 eprom/eeprom parallel bootstrap.............................................................. e-13 e.2.3 eeprom/eprom/ram serial bootstrap........................................................ e-16 e.2.4 ram parallel bootstrap ................................................................................... e-19 e.2.4.1 jump to start of ram ($0050) ................................................................... e-20 e.2.5 maximum ratings ............................................................................................ e-21 e.2.6 thermal characteristics and power considerations......................................... e-22 e.2.7 dc electrical characteristics ....................................................................... e-23 e.2.8 a/d converter characteristics ..................................................................... e-26 e.3 control timing ................................................................................................ e-28 f mc68hc05b32 g mc68hc705b32 g.1 eprom ................................................................................................................g-5 g.1.1 eprom read operation...................................................................................g-5 g.1.2 eprom program operation ............................................................................g-5 g.1.3 eprom/eeprom control register ...............................................................g-6 g.1.4 mask option register .....................................................................................g-8 g.1.5 options register (optr) ...............................................................................g-9 g.2 bootstrap mode ....................................................................................................g-10 g.2.1 erased eprom veri?cation ............................................................................g-13 g.2.2 eprom/eeprom parallel bootstrap..............................................................g-13 g.2.3 serial ram loader...........................................................................................g-16 g.2.3.1 jump to start of ram ($0051) ...................................................................g-16 g.2.4 maximum ratings ............................................................................................g-19 g.2.5 thermal characteristics and power considerations.........................................g-20 g.2.6 dc electrical characteristics ......................................................................g-21 g.2.7 a/d converter characteristics ....................................................................g-24 g.2.8 control timing ..........................................................................................g-26 h high speed operation h.1 dc electrical characteristics ............................................................................... h-2 h.2 a/d converter characteristics .............................................................................. h-3 h.3 control timing for 5v operation ....................................................................... h-4
mc68hc05b6 motorola ix list of figures figure number page number title 1-1 mc68hc05b6 block diagram .................................................................................1-3 2-1 mc68hc05b6 self-check schematic diagram ........................................................2-3 2-2 mc68hc05b6 load program in ram and execute schematic diagram ................2-5 2-3 mc68hc05b6 jump to any address schematic diagram ......................................2-6 2-4 stop and wait ?owcharts....................................................................................2-8 2-5 slow mode divider block diagram ...........................................................................2-10 2-6 oscillator connections ............................................................................................2-13 3-1 memory map of the mc68hc05b6 ........................................................................3-2 4-1 standard i/o port structure.....................................................................................4-2 4-2 eclk timing diagram..............................................................................................4-3 4-3 port logic levels.......................................................................................................4-6 5-1 16-bit programmable timer block diagram ..............................................................5-2 5-2 timer state timing diagram for reset .......................................................................5-13 5-3 timer state timing diagram for input capture ..........................................................5-13 5-4 timer state timing diagram for output compare ......................................................5-14 5-5 timer state timing diagram for timer over?ow.........................................................5-14 6-1 serial communications interface block diagram......................................................6-2 6-2 sci rate generator division .....................................................................................6-4 6-3 data format.............................................................................................................6-5 6-4 sci examples of start bit sampling technique ........................................................6-7 6-5 sci sampling technique used on all bits.................................................................6-7 6-6 arti?cial start following a framing error ...................................................................6-8 6-7 sci start bit following a break.................................................................................6-8 6-8 sci example of synchronous and asynchronous transmission ..............................6-9 6-9 sci data clock timing diagram (m=0) .....................................................................6-12 6-10 sci data clock timing diagram (m=1) .....................................................................6-13 7-1 plm system block diagram.....................................................................................7-1 7-2 plm output waveform examples.............................................................................7-2 7-3 plm clock selection ................................................................................................7-4 8-1 a/d converter block diagram ..................................................................................8-2 8-2 electrical model of an a/d input pin........................................................................8-6 9-1 reset timing diagram..............................................................................................9-1 9-2 watchdog system block diagram ............................................................................9-3 9-3 interrupt ?ow chart..................................................................................................9-8
motorola x mc68hc05b6 list of figures (continued) figure number page number title 10-1 programming model ............................................................................................. 10-1 10-2 stacking order ...................................................................................................... 10-1 11-1 equivalent test load .............................................................................................. 11-2 11-2 run i dd vs internal operating frequency (4.5v, 5.5v) .......................................... 11-4 11-3 run i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v) ........................... 11-4 11-4 wait i dd vs internal operating frequency (4.5v, 5.5v).......................................... 11-4 11-5 wait i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v)........................... 11-5 11-6 increase in i dd vs frequency for a/d, sci systems active, vdd = 5.5v............... 11-5 11-7 i dd vs mode vs internal operating frequency, v dd = 5.5v ................................... 11-5 11-8 run i dd vs internal operating frequency (3 v, 3.6v)............................................. 11-7 11-9 run i dd (sm = 1) vs internal operating frequency (3v,3.6v) ............................... 11-7 11-10 wait i dd vs internal operating frequency (3v, 3.6v)............................................. 11-7 11-11 wait i dd (sm = 1) vs internal operating frequency (3v, 3.6v).............................. 11-8 11-12 increase in i dd vs frequency for a/d, sci systems active, v dd = 3.6v................ 11-8 11-13 i dd vs mode vs internal operating frequency, v dd = 3.6v ................................... 11-8 11-14 timer relationship................................................................................................. 11-13 12-1 52-pin plcc pinout .............................................................................................. 12-1 12-2 64-pin qfp pinout ................................................................................................ 12-2 12-3 56-pin sdip pinout ............................................................................................... 12-3 12-4 52-pin plcc mechanical dimensions .................................................................. 12-4 12-5 64-pin qfp mechanical dimensions..................................................................... 12-5 12-6 56-pin sdip mechanical dimensions.................................................................... 12-6 a-1 mc68hc05b4 block diagram .................................................................................a-2 a-2 memory map of the mc68hc05b4 ........................................................................a-3 b-1 mc68hc05b8 block diagram .................................................................................b-2 b-2 memory map of the mc68hc05b8 ........................................................................b-3 c-1 mc68hc705b5 block diagram .............................................................................. c-2 c-2 memory map of the mc68hc705b5 ..................................................................... c-3 c-3 modes of operation ?ow chart (1 of 2)................................................................... c-9 c-4 modes of operation ?ow chart (2 of 2)................................................................... c-10 c-5 timing diagram with handshake............................................................................ c-11 c-6 eprom(ram) parallel bootstrap schematic diagram ........................................... c-12 c-7 eprom (ram) serial bootstrap schematic diagram ............................................. c-15 c-8 ram parallel bootstrap schematic diagram........................................................... c-16 c-9 eprom parallel bootstrap loader timing diagram ................................................. c-17 c-10 ram parallel loader timing diagram ..................................................................... c-18 d-1 mc68hc05b16 block diagram .............................................................................. d-2 d-2 memory map of the mc68hc05b16 ..................................................................... d-3 e-1 mc68hc705b16 block diagram .............................................................................e-2 e-2 memory map of the mc68hc705b16 ....................................................................e-3
mc68hc05b6 motorola xi list of figures (continued) figure number page number title e-3 modes of operation ?ow chart (1 of 2) ................................................................... e-11 e-4 modes of operation ?ow chart (2 of 2) ................................................................... e-12 e-5 timing diagram with handshake ............................................................................ e-13 e-6 parallel eprom loader timing diagram ................................................................. e-14 e-7 eprom parallel bootstrap schematic diagram...................................................... e-15 e-8 ram/eprom/eeprom serial bootstrap schematic diagram ............................... e-17 e-9 parallel ram loader timing diagram ...................................................................... e-19 e-10 ram parallel bootstrap schematic diagram ........................................................... e-20 e-11 equivalent test load ............................................................................................... e-22 e-12 timer relationship .................................................................................................. e-30 f-1 mc68hc05b32 block diagram ...............................................................................f-2 f-2 memory map of the mc68hc05b32 ......................................................................f-3 g-1 mc68hc705b32 block diagram ............................................................................ g-2 g-2 memory map of the mc68hc705b32 ................................................................... g-3 g-3 modes of operation ?ow chart (1 of 2) ................................................................... g-11 g-4 modes of operation ?ow chart (2 of 2) ................................................................... g-12 g-5 timing diagram with handshake ............................................................................ g-14 g-6 parallel eprom loader timing diagram ................................................................. g-14 g-7 eprom parallel bootstrap schematic diagram...................................................... g-15 g-8 ram load and execute schematic diagram ........................................................... g-17 g-9 parallel ram loader timing diagram ...................................................................... g-18 g-10 equivalent test load ............................................................................................... g-20 g-11 timer relationship .................................................................................................. g-28 h-1 timer relationship .................................................................................................. h-4
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mc68hc05b6 motorola xiii list of tables table number page number title 1-1 data sheet appendices...........................................................................................1-1 2-1 mode of operation selection ...................................................................................2-1 2-2 mc68hc05b6 self-check results............................................................................2-2 3-1 eeprom control bits description ...........................................................................3-4 3-2 register outline.......................................................................................................3-8 3-3 irq sensitivity.........................................................................................................3-9 4-1 i/o pin states ..........................................................................................................4-2 6-1 method of receiver wake-up ...................................................................................6-11 6-2 sci clock on sclk pin ...........................................................................................6-13 6-3 first prescaler stage ...............................................................................................6-18 6-4 second prescaler stage (transmitter) .....................................................................6-18 6-5 second prescaler stage (receiver)..........................................................................6-19 6-6 sci baud rate selection ..........................................................................................6-20 8-1 a/d clock selection .................................................................................................8-4 8-2 a/d channel assignment.........................................................................................8-5 9-1 effect of reset, por, stop and wait................................................................9-5 9-2 interrupt priorities ...................................................................................................9-7 9-3 irq sensitivity.........................................................................................................9-9 10-1 mul instruction.....................................................................................................10-5 10-2 register/memory instructions...............................................................................10-5 10-3 branch instructions ...............................................................................................10-6 10-4 bit manipulation instructions.................................................................................10-6 10-5 read/modify/write instructions .............................................................................10-7 10-6 control instructions...............................................................................................10-7 10-7 instruction set (1 of 2)...........................................................................................10-8 10-8 instruction set (2 of 2)...........................................................................................10-9 10-9 m68hc05 opcode map.........................................................................................10-10 11-1 maximum ratings ..................................................................................................11-1 11-2 package thermal characteristics...........................................................................11-2 11-3 dc electrical characteristics for 5v operation.......................................................11-3 11-4 dc electrical characteristics for 3.3v operation....................................................11-6 11-5 a/d characteristics for 5v operation .....................................................................11-9 11-6 a/d characteristics for 3.3v operation ..................................................................11-10 11-7 control timing for 5v operation .............................................................................11-11 11-8 control timing for 3.3v operation ..........................................................................11-12
motorola xiv mc68hc05b6 list of tables (continued) table number page number title 13-1 mc order numbers ............................................................................................... 13-1 13-2 eproms for pattern generation ........................................................................... 13-2 a-1 register outline ......................................................................................................a-4 b-1 register outline ......................................................................................................b-4 c-1 register outline ..................................................................................................... c-4 c-2 mode of operation selection .................................................................................. c-8 c-3 bootstrap vector targets in ram............................................................................ c-14 c-4 additional dc electrical characteristics for mc68hc705b5 .................................. c-19 c-5 additional control timing for mc68hc705b5 ......................................................... c-19 d-1 register outline ..................................................................................................... d-4 e-1 register outline ......................................................................................................e-4 e-2 eprom control bits description .............................................................................e-6 e-3 eeprom control bits description ...........................................................................e-7 e-4 mode of operation selection ...................................................................................e-10 e-5 bootstrap vector targets in ram.............................................................................e-18 e-6 maximum ratings ....................................................................................................e-21 e-7 package thermal characteristics.............................................................................e-22 e-8 dc electrical characteristics for 5v operation ........................................................e-23 e-9 dc electrical characteristics for 3.3v operation .....................................................e-25 e-10 a/d characteristics for 5v operation .......................................................................e-26 e-11 a/d characteristics for 3.3v operation ....................................................................e-27 e-12 control timing for 5v operation...............................................................................e-28 e-13 control timing for 3.3v operation............................................................................e-29 f-1 register outline ......................................................................................................f-4 g-1 register outline ..................................................................................................... g-4 g-2 eprom control bits description ............................................................................ g-6 g-3 eeprom control bits description .......................................................................... g-7 g-4 mode of operation selection .................................................................................. g-10 g-5 bootstrap vector targets in ram............................................................................ g-16 g-6 maximum ratings ................................................................................................... g-19 g-7 package thermal characteristics............................................................................ g-20 g-8 dc electrical characteristics for 5v operation ....................................................... g-21 g-9 dc electrical characteristics for 3.3v operation .................................................... g-23 g-10 a/d characteristics for 5v operation ...................................................................... g-24 g-11 a/d characteristics for 3.3v operation ................................................................... g-25 g-12 control timing for 5v operation.............................................................................. g-26 g-13 control timing for operation at 3.3v....................................................................... g-27 h-1 ordering information.............................................................................................. h-1 h-2 dc electrical characteristics for 5v operation ....................................................... h-2 h-3 a/d characteristics for 5v operation ...................................................................... h-3
mc68hc05b6 motorola 1-1 introduction 1 1 introduction the mc68hc05b6 microcomputer (mcu) is a member of motorola s mc68hc05 f amily of lo w-cost single chip microcomputers . this 8-bit mcu contains an on-chip oscillator , cpu, ram, r om, eepr om, a/d con verter , pulse length modulated outputs , i/o , ser ial comm unications interface, programmab le timer system and w atchdog. the fully static design allo ws operation at frequencies do wn to dc to fur ther reduce the already lo w pow er consumption to a f ew micro-amps. this data sheet is str uctured such that de vices similar to the mc68hc05b6 are descr ibed in a set of appendices (see table 1-1). table 1-1 data sheet appendices device appendix differences from mc68hc05b6 mc68hc05b4 a 4k bytes rom; no eeprom mc68hc05b8 b 7.25k bytes rom mc68hc705b5 c 6k bytes eprom; self-check replaced by bootstrap ?rmware; no eeprom mc68hc05b16 d 16k bytes rom; increased ram and self-check rom mc68hc705b16 e 16k bytes eprom; increased ram; self-check replaced by bootstrap ?rmware; modi?ed power-on reset routine mc68hc05b32 f 32k bytes rom; no page zero rom; increased ram mc68hc705b32 g 32k bytes eprom; no page zero rom; increased ram; self-check mode replaced by bootstrap ?rmware
motorola 1-2 mc68hc05b6 introduction 1 1.1 features hardware features ? fully static design featuring the industry standard m68hc05 family cpu core ? on chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (slow mode) ? 2.1 mhz internal operating frequency at 5v; 1.0 mhz at 3v ? 176 bytes of ram ? 5936 bytes of user rom plus 14 bytes of user vectors ? 256 bytes of byte erasable eeprom with internal charge pump and security bit ? write/erase protect bit for 224 of the 256 bytes eeprom ? self test/bootstrap mode ? power saving stop, wait and slow modes ? three 8-bit parallel i/o ports and one 8-bit input-only port ? software option available to output the internal e-clock to port pin pc2 ? 16-bit timer with 2 input captures and 2 output compares ? computer operating properly (cop) watchdog timer ? ser ial comm unications interf ace system (sci) with independent tr ansmitter/receiv er baud r ate selection; receiver wake-up function for use in multi-receiver systems ? 8 channel a/d converter ? 2 pulse length modulation systems which can be used as d/a converters ? one interrupt request input plus 4 on-board hardware interrupt sources ? availab le in 52-pin plastic leaded chip carr ier (plcc), 64-pin quad ?at pac k (qfp) and 56-pin shrink dual in line (sdip) packages ? complete de v elopment system suppor t a vailab le using the mmds05 de v elopment station with the m68hc05bem emulation module or the m68hc05bevs evaluation system 1.2 mask options for the mc68hc05b6 the mc68hc05b6 has three mask options that are prog rammed during manuf acture and m ust be speci?ed on the order form. ? power-on-reset delay (t porl ) = 16 or 4064 cycles
mc68hc05b6 motorola 1-3 introduction 1 ? automatic watchdog enable/disable following a power-on or external reset ? watchdog enable/disable during wait mode warning: it is recommended that an e xter nal cloc k is alw a ys used if t porl is set to 16 cycles . this will pre v ent an y prob lems ar ising with oscillator stability when the de vice is put into stop mode. figure 1-1 mc68hc05b6 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 5950 bytes self check rom (including 14 bytes user vectors)
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mc68hc05b6 motorola 2-1 modes of operation and pin descriptions 2 2 modes of operation and pin descriptions 2.1 modes of operation the mc68hc05b6 mcu has two modes of operation, namely single chip and self check modes. table 2-1 shows the conditions required to enter each mode on the rising edge of reset. 2.1.1 single chip mode this is the nor mal oper ating mode of the mc68hc05b6. in this mode the de vice functions as a self-contained microcomputer (mcu) with all on-board per ipherals , including the three 8-bit i/o por ts and the 8-bit input-only por t, availab le to the user . all address and data activity occurs within the mcu. 2.1.2 self-check mode the self-chec k function a vailab le on the mc68hc05b6 pro vides an inter nal capability to deter mine if the de vice is functional. self-chec k is perf or med using the circuit sho wn in figure 2-1. por t c pins pc0Cpc3 are monitored f or the self-chec k results (light emitting diodes are sho wn but other de vices could be used), and are inter preted as descr ibed in t ab le 2-2. the self-chec k mode table 2-1 mode of operation selection irq pin tcap1 pin pd3 pd4 mode v ss to v dd v ss to v dd x x single chip 2v dd v dd 0 x self-check 2v dd v dd 1 0 serial ram loader 2v dd v dd 1 1 jump to any address
motorola 2-2 mc68hc05b6 modes of operation and pin descriptions 2 is entered b y applying 2 x v dd dc (via a 4.7k? resistor) to the irq pin and 5v dc input (via a 4.7k? resistor) to the tcap1 pin and then depressing the reset s witch to e x ecute a reset. after reset, the follo wing tests are perf or med automatically and once completed the y contin ually repeat. a good device will e xhibit ?ashing leds; a bad de vice will be indicated b y the leds holding at one v alue. i/0 functionally exercises ports a, b, c and d ram counter test for each ram byte rom exclusive or with odd ones parity result timer tracks counter registers and checks icf1, icf2, ocf1, ocf2 and tof ?ags sci transmission test; check for rdrf, tdre, tc and fe ?ags a/d check a/d functionality on internal channels: vrl, vrh and (vrl + vrh)/2 eeprom this test is optional; it executes a write/erase test of the 256 bytes eeprom (available only for the mc68hc05b6 version), and then deactivates the security bit. plm checks the plm basic functionality interrupts tests external timer and sci interrupts watchdog tests the watchdog table 2-2 mc68hc05b6 self-check results pc3 pc2 pc1 pc0 remarks 1 0 0 1 bad port 0 1 1 0 bad port 1 0 1 0 bad ram 1 0 1 1 bad rom 1 1 0 0 bad timer 1 1 0 1 bad sci 1 1 1 0 bad a/d 0 0 0 0 bad eeprom (or other if b4) 0 0 0 1 bad plm 0 0 1 0 bad interrupts 0 0 1 1 bad watchdog flashing good device all others bad device, bad port etc. 0 indicates led on; 1 indicates led off
mc68hc05b6 motorola 2-3 modes of operation and pin descriptions 2 figure 2-1 mc68hc05b6 self-check schematic diagram 6 40 51 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vrl vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 tcmp1 sclk plmb plma tdo rdi vpp1 nc reset nc vrh vdd 18 50 52 20 21 2 3 4 5 9 11 12 13 14 24 25 26 27 28 29 30 31 16 17 19 23 1 22 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 41 7 0.01 f 10 nf 47 f 10 m? 4 mhz 22 pf 4k7 ? 4k7 ? 680 ? 22 pf 4k7 ? 4k7 ? 680 ? 680 ? 680 ? bc239 p1 gnd +5v 2xv dd reset eeprom tested eeprom not tested 15 8 10 note: for the mc68hc05b4, switches on pb5 and pb6 have no effect all resistors are 10 k?, unless otherwise stated. mc68hc05b6 (52-pin package)
motorola 2-4 mc68hc05b6 modes of operation and pin descriptions 2 2.2 serial ram loader the load prog r am in ram and e x ecute mode is entered if the f ollo wing conditions are satis?ed when the reset pin is released to v dd . the f or mat used is identical to the f or mat used f or the mc68hc805c4. the sec bit in the options register must be inactive, i.e. set to 1. C irq at 2xv dd C tcap1 at v dd C pd3 at v dd for at least 30 machine cycles after reset C pd4 at v ss for at least 30 machine cycles after reset in the load prog r am in ram and e xecute routine, user progr ams are loaded into mcu ram via the sci por t and then e x ecuted. data is loaded sequentially , star ting at ram location $0050, until the last b yte is loaded. prog r am control is then tr ansf erred to the ram prog ram star ting at location $0051. the ?rst b yte loaded is the count of the total n umber of b ytes in the prog r am plus the count byte. the program star ts at the second b yte in ram. during the ?rmware initialization stage, the sci is con?gured f or the nrz data f or mat (idle line , star t bit, eight data bits and stop bit). the baud r ate is 9600 with a 4 mhz cr ystal. a program to conver t ascii s-records to the f ormat required by the ram loader is available from motorola. if immediate e x ecution is not desired after loading the ram prog r am, it is possib le to hold off ex ecution. this is accomplished b y setting the b yte count to a v alue that is g reater than the o verall length of the loaded data. when the last b yte is loaded, the ?rmware will halt operation expecting additional data to arr ive . at this point, the reset s witch is placed in the reset position which will reset the mcu, but k eep the ram prog r am intact. all routines can no w be entered from this state , including the one which will execute the program in ram (see section 2.3). to load a program in the eeprom, the load program in ram and execute function is also used. in this instance the process involves two distinct steps. firstly, the ram is loaded with a program which will control the loading of the eepr om, and when the ram contents are e x ecuted, the mcu is instructed to load the eeprom. the erased state of the eeprom is $ff. figure 2-2 shows the schematic diagram of the circuit required for the serial ram loader. 2.3 jump to any address the jump to any address mode is entered when the reset pin is released to v dd , if the following conditions are satis?ed: C irq at 2xv dd C tcap1 at v dd C pd3 at v dd for at least 30 machine cycles after reset C pd4 at v dd for at least 30 machine cycles after reset
mc68hc05b6 motorola 2-5 modes of operation and pin descriptions 2 this function allo ws e x ecution of prog r ams pre viously loaded in ram or eepr om using the methods outlined in section 2.2. to ex ecute the jump to an y address function, data input at por t a has to be $cc and data input at por t b and por t c should represent the msb and lsb respectiv ely , of the address to jump to f or ex ecution of the user prog r am. a schematic diag r am of the circuit required is sho wn in figure 2-3 . figure 2-2 mc68hc05b6 load progr am in ram and e xecute schematic diagram 32 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset vdd 18 24 25 26 27 28 29 30 31 16 17 19 41 10 k? 0.01 f 10 nf 47 f 10 m? 4 mhz 22 pf 10 k? 22 pf p1 gnd +5v 2xv dd reset 10 vrh vrl vpp1 plma plmb tcmp1 rdi tdo nc nc rs232 level translator suggested: mc145406 or max232 9600 bd rs232 sclk 10 k? 10 k? 10 k? 11 9 22 8 7 40 20 21 51 1 23 2 3 4 5 12 13 14 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 6 15 50 52 optional 3 x 10 k? connect as required for the application connect as required for the application mc68hc05b6 (52-pin package)
motorola 2-6 mc68hc05b6 modes of operation and pin descriptions 2 figure 2-3 mc68hc05b6 jump to any address schematic diagram 32 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset vdd 18 24 25 26 27 28 29 30 31 16 17 19 41 10 k? 0.01 f 10 nf 47 f 10 m? 4 mhz 22 pf 10 k? 22 pf p1 gnd +5v 2xv dd reset 10 vrh vrl vpp1 plma plmb tcmp1 rdi tdo nc nc sclk 10 k? 10 k? 10 k? 11 9 22 8 7 40 20 21 51 1 23 2 3 4 5 12 13 14 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 6 15 50 52 optional 3 x 10 k? connect as required for the application 8 x 10 k? optional (see note) 8 x 10 k? 8 x 10 k? msb lsb select required address note: these eight resistors are optional; direct connection is possib le if pins p a0-p a7, pb0-pb7 and pc0-pc7 are kept in input mode during application. mc68hc05b6 (52-pin package)
mc68hc05b6 motorola 2-7 modes of operation and pin descriptions 2 2.4 low power modes the st op and w ait instr uctions ha v e diff erent eff ects on the prog rammab le timer , the ser ial comm unications interf ace , the w atchdog system, the eepr om and the a/d con verter . these different effects are described in the following sections. 2.4.1 stop the stop instr uction places the mcu in its lo west pow er consumption mode . in st op mode, the inter nal oscillator is tur ned off , halting all inter nal processing including timer , ser ial communications interf ace and the a/d con ver ter (see ?o wchar t in figure 2-4). the only w ay for the mcu to w ak e-up from the st op mode is b y receipt of an e xternal interr upt or b y the detection of a reset (logic low on reset pin or a power-on reset). dur ing st op mode , the i-bit in the ccr is cleared to enab le e xter nal interr upts (see section 10.1.5). the sm bit is cleared to allo w nominal speed oper ation f or the 4064 cycles count while exiting stop mode (see section 2.4.3). all other registers and memor y remain unaltered and all input/output lines remain unchanged. this contin ues until an e xter nal interr upt ( irq ) or reset is sensed, at which time the inter nal oscillator is turned on. the external interr upt or reset causes the prog ram counter to vector to the corresponding locations ($1ffa, b and $1ffe, f respectively). when leaving stop mode, a t porl internal cycles delay is provided to give the oscillator time to stabilise bef ore releasing cpu oper ation. this dela y is selectab le via a mask option to be either 16 or 4064 cycles . the cpu will resume oper ation by ser vicing the interr upt that w ak es it up , or by fetching the reset vector, if reset wakes it up. warning: if t porl is selected to be 16 cycles , it is recommended that an e xternal clock signal is used to avoid problems with oscillator stability while the device is in stop mode. note: the stac king corresponding to an e ventual interr upt to go out of st op mode will only be executed when going out of stop mode. the f ollo wing list summar iz es the eff ect of st op mode on the individual modules of the mc68hc05b6. C the watchdog timer is reset; refer to section 9.1.4.1 C the eeprom acts as read-only memory (rom); refer to section 3.6 C all sci activity stopped; refer to section 6.13 C the timer stops counting; refer to section 5.6 C the plm outputs remain at current level; refer to section 7.2 C the a/d converter is disabled; refer to section 8.3 C the i-bit in the ccr is cleared
motorola 2-8 mc68hc05b6 modes of operation and pin descriptions 2 figure 2-4 stop and wait ?owcharts timer interrupt? irq external interrupt? sci interrupt? stop oscillator and all clocks. clear i bit. stop wait reset? irq external interrupt? gener ate w atchdog interrupt reset? watchdog active? (1) fetch reset vector or (2) service interrupt: a. stack b. set i-bit c. vector to interrupt routine (1) fetch reset vector or (2) service interrupt: a. stack b. set i-bit c. vector to interrupt routine turn on oscillator. wait for time delay to stabilise restar t processor cloc k yes no yes yes yes yes yes yes no no no no no no oscillator activ e . timer , sci, a/d , eepr om cloc ks activ e. processor cloc ks stopped clear i-bit
mc68hc05b6 motorola 2-9 modes of operation and pin descriptions 2 2.4.2 wait the w ait instr uction places the mcu in a lo w po w er consumption mode , b ut w ait mode consumes more po w er than st op mode . all cpu action is suspended and the w atchdog is disabled, but the timer , a/d and sci systems remain activ e and operate as normal (see ?owchart in figure 2-4). all other memory and registers remain unaltered and all parallel input/output lines remain unchanged. the prog r amming or er ase mechanism of the eepr om is also unaff ected, as well as the charge pump high voltage generator. dur ing w ait mode the i-bit in the ccr is cleared to enab le all interr upts . the inte bit in the miscellaneous register (section 2.5) is not aff ected by wait mode. when any interr upt or reset is sensed, the program counter vectors to the locations containing the start address of the interrupt or reset service routine. any irq, timer (over?ow , input capture or output compare) or sci interr upt (in addition to a logic low on the reset pin) causes the processor to exit wait mode. if a non-reset e xit from w ait mode is perf ormed (i.e. timer over?ow interrupt e xit), the state of the remaining systems will be unchanged. if a reset exit from wait mode is performed the entire system reverts to the disabled reset state. note: the stac king corresponding to an e ventual interr upt to lea ve w ait mode will only be executed when leaving wait mode. the following list summarizes the effect of wait mode on the modules of the mc68hc05b6. C the watchdog timer functions according to the mask option selected; refer to section 9.1.4.2 C the eeprom is not affected; refer to section 3.7 C the sci is not affected; refer to section 6.14 C the timer is not affected; refer to section 5.7 C the plm is not affected; refer to section 7.4 C the a/d converter is not affected; refer to section 8.4 C the i-bit in the ccr is cleared 2.4.2.1 power consumption during wait mode pow er consumption dur ing w ait mode depends on ho w man y systems are activ e . the po wer consumption will be highest when all the systems (a/d, timer, eeprom and sci) are active, and low est when the eepr om er ase and prog r amming mechanism, sci and a/d are disab led. the timer cannot be disab led in w ait mode . it is impor tant that bef ore enter ing w ait mode , the progr ammer sets the rele v ant control bits f or the individual modules to re?ect the desired functionality during wait mode. power consumption may be further reduced by the use of slow mode.
motorola 2-10 mc68hc05b6 modes of operation and pin descriptions 2 2.4.3 slow mode the slo w mode function is controlled b y the sm bit in the miscellaneous register at location $000c . it allo ws the user to inser t, under softw are control, an e xtr a divide-b y-16 betw een the oscillator and the inter nal clock driv er (see figure 2-5). this f eature per mits a slo w do wn of all the internal oper ations and thus reduces po w er consumption. the slo w mode function should not be enab led while using the a/d con verter or while erasing/programming the eeprom unless the internal a/d rc oscillator is turned on. 2.4.3.1 miscellaneous register sm slow mode 1 (set) C the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sections of the device, including sci, a/d and timer. 0 (clear) C the system runs at normal bus speed (f osc /2). the sm bit is cleared by external or power-on reset. the sm bit is automatically cleared when entering stop mode. note: the bits sho wn shaded in the abo v e representation are e xplained individually in the relevant sections of this man ual. the complete register plus an e xplanation of each bit can be found in section 3.8. figure 2-5 slow mode divider block diagram address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000? osc1 pin osc2 pin oscillator f osc control logic smCbit f osc /2 2 16 main internal clock f osc /32 (bit 1, $000c)
mc68hc05b6 motorola 2-11 modes of operation and pin descriptions 2 2.5 pin descriptions 2.5.1 vdd and vss pow er is supplied to the microcontroller using these tw o pins . vdd is the positiv e supply and vss is ground. it is in the nature of cmos designs that v ery fast signal tr ansitions occur on the mcu pins . these short rise and fall times place very high short-dur ation current demands on the po wer supply. to prevent noise problems , special care m ust be taken to provide good power supply by-passing at the mcu . by-pass capacitors should ha v e good high-frequency char acter istics and be as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 2.5.2 irq this is an input-only pin f or e xter nal interr upt sources . interr upt tr igger ing is selected using the intp and intn bits in the miscellaneous register , to be one of four options detailed in table 9-3. in addition, the e xter nal interr upt f acility ( irq ) can be disab led using the inte bit in the miscellaneous register (see section 3.8). it is only possib le to change the interr upt option bits in the miscellaneous register while the i-bit is set. selecting a diff erent interr upt option will automatically clear any pending interrupts. further details of the external interrupt procedure can be found in section 9.2.3.1. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. 2.5.3 reset this active lo w i/o pin is used to reset the mcu . applying a logic z ero to this pin f orces the de vice to a kno wn star t-up state . an e xter nal rc-circuit can be connected to this pin to gener ate a pow er-on-reset (por) if required. in this case , the time constant m ust be g reat enough (at least 100ms) to allo w the oscillator circuit to stabilise . this input has an inter nal schmitt tr igger to improv e noise imm unity . when a reset condition occurs inter nally , i.e . from the cop w atchdog, the reset pin pro vides an activ e-lo w open dr ain output signal that ma y be used to reset e xternal hardware. 2.5.4 tcap1 the tcap1 input controls the input capture 1 function of the on-chip prog rammab le timer system.
motorola 2-12 mc68hc05b6 modes of operation and pin descriptions 2 2.5.5 tcap2 the tcap2 input controls the input capture 2 function of the on-chip prog rammab le timer system. 2.5.6 tcmp1 the tcmp1 pin is the output of the output compare 1 function of the timer system. 2.5.7 tcmp2 the tcmp2 pin is the output of the output compare 2 function of the timer system. 2.5.8 osc1, osc2 these pins pro vide control input f or an on-chip oscillator circuit. a cr ystal, cer amic resonator or exter nal cloc k signal connected to these pins supplies the oscillator cloc k. the oscillator frequency (f osc ) is divided b y tw o to giv e the inter nal b us frequency (f op ). there is also a softw are option which introduces an additional divide b y 16 into the oscillator cloc k, giving an inter nal b us frequency of f osc /32. 2.5.8.1 crystal the circuit sho wn in figure 2-6(a) is recommended when using either a cr ystal or a cer amic resonator . figure 2-6(d) lists the recommended capacitance and f eedbac k resistance v alues. the inter nal oscillator is designed to interf ace with an a t-cut parallel-resonant quartz crystal resonator in the frequency range speci?ed for f osc (see section 11.5). use of an external cmos oscillator is recommended when cr ystals outside the speci?ed r anges are to be used. the cr ystal and associated components should be mounted as close as possib le to the input pins to minimise output distor tion and star t-up stabilisation time . the man uf acturer of the par ticular crystal being considered should be consulted for speci?c information. 2.5.8.2 ceramic resonator a cer amic resonator ma y be used instead of a cr ystal in cost sensitiv e applications . the circuit sho wn in figure 2-6(a) is recommended when using either a cr ystal or a cer amic resonator . figure 2-6(d) lists the recommended capacitance and f eedbac k resistance v alues . the man uf acturer of the par ticular cer amic resonator being considered should be consulted f or speci?c inf or mation.
mc68hc05b6 motorola 2-13 modes of operation and pin descriptions 2 2.5.8.3 external clock an external cloc k should be applied to the osc1 input, with the osc2 pin left unconnected, as sho wn in figure 2-6(c). the t oxov or t ilch speci?cations (see section 11.5) do not apply when using an external clock input. the equivalent speci?cation of the external clock source should be used in lieu of t oxov or t ilch . figure 2-6 oscillator connections ceramic resonator 2 C 4 mhz unit r s (typ) 10 c 0 40 pf c 1 4.3 pf c osc1 30 pf c osc2 30 pf r p 1 C 10 m? q 1250 crystal 2 mhz 4 mhz unit r s (max) 400 75 c 0 5 7 pf c 1 8 12 nf c osc1 15 C 40 15 C 30 pf c osc2 15 C 30 15 C 25 pf r p 10 10 m? q 30 000 40 000 osc1 osc2 r p mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 (d) typical crystal and ceramic resonator parameters (c) external clock source connections (b) crystal equivalent circuit (a) crystal/ceramic resonator oscillator connections
motorola 2-14 mc68hc05b6 modes of operation and pin descriptions 2 2.5.9 rdi (receive data in) the rdi pin is the input pin of the sci receiver. 2.5.10 tdo (transmit data out) the tdo pin is the output pin of the sci transmitter. 2.5.11 sclk the sclk pin is the clock output pin of the sci transmitter. 2.5.12 plma the plma pin is the output of pulse length modulation converter a. 2.5.13 plmb the plmb pin is the output of pulse length modulation converter b. 2.5.14 vpp1 the vpp1 pin is the output of the charge pump for the eeprom1 array. 2.5.15 vrh the vrh pin is the positive reference voltage for the a/d converter. 2.5.16 vrl the vrl pin is the negative reference voltage for the a/d converter. 2.5.17 pa0 C pa7/pb0 C pb7/pc0 C pc7 these 24 i/o lines compr ise por ts a, b and c . the state of an y pin is softw are programmable, and all the pins are con?gured as inputs during power-on or reset. under software control the pc2 pin can output the internal e-clock (see section 4.2). 2.5.18 pd0/an0Cpd7/an7 this 8-bit input only por t (d) shares its pins with the a/d con verter . when enab led, the a/d conver ter uses pins pd0/an0 C pd7/an7 as its analog inputs . on reset, the a/d con ver ter is disabled which forces the port d pins to be input only port pins (see section 8.5).
mc68hc05b6 motorola 3-1 memory and registers 3 3 memory and registers the mc68hc05b6 mcu is capab le of addressing 8192 b ytes of memor y and registers with its program counter . the memor y map includes 5950 b ytes of user r om (including user v ectors), 432 bytes of self check rom, 176 bytes of ram and 256 bytes of eeprom. 3.1 registers all the i/o , control and status registers of the mc68hc05b6 are contained within the ?rst 32-b yte bloc k of the memor y map , as sho wn in figure 3-1. the miscellaneous register is sho wn in section 3.8 as this register contains bits which are relevant to several modules. 3.2 ram the user ram compr ises 176 b ytes of memor y , from $0050 to $00ff . this is shared with a 64 byte stack area. the stack begins at $00ff and may extend down to $00c0. note: using the stac k area f or data stor age or tempor ar y w or k locations requires care to pre v ent the data from being o v erwr itten due to stac king from an interr upt or subroutine call. 3.3 rom the user rom consists of 5950 bytes of rom mapped as follows: ? 48 bytes of page zero rom from $0020 to $004f ? 5888 bytes of user rom from $0800 to $1eff ? 14 bytes of user vectors from $1ff2 to $1fff
motorola 3-2 mc68hc05b6 memory and registers 3 3.4 self-check rom there are tw o areas of self-chec k r om (r omi and r omii) located from $0200 to $02bf (192 bytes) and $1f00 to $1fef (240 bytes) respectively. figure 3-1 memory map of the mc68hc05b6 $1ffeCf $1ff6C7 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register user vectors (14 bytes) $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (5888 bytes) self-check rom ii (240 bytes) $0800 $1ff2C3 optr (1 byte) non protected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b6 registers sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff4C5 $1ff8C9 $1ffaCb $1ffcCd
mc68hc05b6 motorola 3-3 memory and registers 3 3.5 eeprom the user eepr om consists of 256 b ytes of memor y located from address $0100 to $01ff . 255 bytes are general purpose and 1 byte is used by the option register. the non-volatile eeprom is byte erasable. an inter nal charge pump pro vides the eepr om v oltage (v pp1 ), which remo v es the need to supply a high v oltage for er ase and prog ramming functions . the charge pump is a capacitor/diode ladder networ k which will giv e a v er y high impedance output of around 20-30 m?. the v oltage of the charge pump is visib le at the vpp1 pin. dur ing nor mal oper ation of the de vice , where programming/er asing of the eepr om arra y will occur , vpp1 should ne v er be connected to either vdd or vss as this could pre v ent the charge pump reaching the necessar y programming voltage. where it is considered dangerous to lea v e vpp1 unconnected f or reasons of e xcessive noise in a system, it ma y be tied to v dd ; this will protect the eepr om data b ut will also increase po wer consumption, and theref ore it is recommended that the protect bit function is used f or regular protection of eeprom data (see section 3.5.5). in order to achie v e a higher deg ree of secur ity f or stored data, there is no capability f or b ulk or ro w erase operations. the eeprom control register ($0007) provides control of the eeprom programming and erase operations. warning: the vpp1 pin should ne v er be connected to vss , as this could cause per manent damage to the device. 3.5.1 eeprom control register eclk see section 4.3 for a description of this bit. e1era eeprom erase/programming bit pro viding the e1la t and e1pgm bits are at logic one , this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) C an erase operation will take place. 0 (clear) C a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000
motorola 3-4 mc68hc05b6 memory and registers 3 e1lat eeprom programming latch enable bit 1 (set) C address and data can be latched into the eeprom for further program or erase operations, providing the e1pgm bit is cleared. 0 (clear) C data can be read from the eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is 0. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1la t bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm eeprom charge pump enable/disable 1 (set) C internal charge pump generator switched on. 0 (clear) C internal charge pump generator switched off. when the charge pump gener ator is on, the resulting high v oltage is applied to the eepr om arr ay. this bit cannot be set bef ore the data is selected, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summar y of the eff ects of setting/clear ing bits 0, 1 and 2 of the control register are giv e in t ab le 3-1. note: all combinations are not sho wn in the above table , since the e1pgm and e1era bits are cleared when the e1lat bit is at zero, and will result in a read condition. table 3-1 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
mc68hc05b6 motorola 3-5 memory and registers 3 3.5.2 eeprom read operation t o be ab le to read from eepr om, the e1la t bit has to be at logic z ero , as sho wn in t able 3-1. while this bit is at logic z ero , the e1pgm bit and the e1era bit are per manently reset to z ero and the 256 b ytes of eepr om ma y be read as if it w ere a nor mal r om area. the inter nal charge pump generator is automatically switched off since the e1pgm bit is reset. if a read operation is executed while the e1lat bit is set (erase or programming sequence), data resulting from the operation will be $ff. note: when not perf or ming an y prog r amming or er ase oper ation, it is recommended that eeprom should remain in the read mode (e1lat = 0) 3.5.3 eeprom erase operation to erase the contents of a byte of the eeprom, the following steps should be taken: 1 set the e1lat bit. 2 set the e1era bit (1& 2 may be done simultaneously with the same instruction). 3 write address/data to the eeprom address to be erased. 4 set the e1pgm bit. 5 wait for a time t era1 . 6 reset the e1lat bit (to logic zero). while an er ase oper ation is being perf or med, an y access of the eepr om arr a y will not be successful. the erased state of the eeprom is $ff and the programmed state is $00. note: data wr itten to the address to be er ased is not used, theref ore its v alue is not signi?cant. if a second w ord is to be er ased, it is impor tant that the e1la t bit be reset bef ore restarting the er asing sequence otherwise an y wr ite to a ne w address will ha v e no eff ect. this condition pro vides a higher degree of security for the stored data. user programs must be r unning from the ram or r om as the eepr om will hav e its address and data buses latched.
motorola 3-6 mc68hc05b6 memory and registers 3 3.5.4 eeprom programming operation to program a byte of eeprom, the following steps should be taken: 1 set the e1lat bit. 2 write address/data to the eeprom address to be programmed. 3 set the e1pgm bit. 4 wait for time t prog1 . 5 reset the e1lat bit (to logic zero). while a programming operation is being performed, any access of the eeprom array will not be successful. warning: to program a byte correctly, it has to have been previously erased. if a second w ord is to be prog r ammed, it is impor tant that the e1la t bit be reset bef ore restarting the prog r amming sequence otherwise an y wr ite to a ne w address will ha v e no eff ect. this condition provides a higher degree of security for the stored data. user programs must be r unning from the ram or r om as the eepr om will hav e its address and data buses latched. note: 224 b ytes of eepr om (address $0120 to $01ff) can be prog r am and er ase protected under the control of bit 1 of the optr register detailed in section 3.5.5. 3.5.5 options register (optr) this register (optr), located at $0010, contains the secure and protect functions f or the eepr om and allo ws the user to select options in a non-v olatile manner . the contents of the optr register are loaded into data latches with each power-on or external reset. (1) this register is implemented in eeprom; therefore reset has no effect on the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) $0100 ee1p sec not affected
mc68hc05b6 motorola 3-7 memory and registers 3 ee1p C eeprom protect bit in order to achie v e a higher deg ree of protection, the eepr om is eff ectiv ely split into tw o parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; par t 2 (224 b ytes from $0120 to $01ff) is protected b y the ee1p bit of the options register. 1 (set) C par t 2 of the eepr om arr a y is not protected; all 256 b ytes of eepr om can be accessed f or an y read, er ase or prog r amming oper ations 0 (clear) C part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful when this bit is set to 1 (er ased), the protection will remain until the ne xt po w er-on or e xternal reset. ee1p can only be written to 0 when the elat bit in the eeprom control register is set. sec C security bit this high security bit allows the user to secure the eeprom data from external accesses. when the sec bit is at 0, the eepr om contents are secured b y preventing any entr y to test mode . the only way to er ase the sec bit to 1 e xter nally is to enter self-chec k mode , at which time the entire eepr om contents will be er ased. when the sec bit is changed, its ne w value will have no effect until the next external or power-on reset. 3.6 eeprom during stop mode when entering stop mode , the eepr om is automatically set to the read mode and the vpp1 high voltage charge pump generator is automatically disabled. 3.7 eeprom during wait mode the eepr om is not aff ected b y w ait mode . an y prog ram/er ase oper ation will contin ue as in normal operating mode . the charge pump is not aff ected by wait mode, theref ore it is possib le to wait the t era1 erase time or t prog1 programming time in wait mode. under nor mal oper ating conditions , the charge pump gener ator is dr iv en b y the inter nal cpu clocks . when the oper ating frequency is lo w, e.g. during wait mode , the cloc king should be done by the internal a/d rc oscillator. the rc oscillator is enabled by setting the adrc bit of the a/d status/control register at $0009.
motorola 3-8 mc68hc05b6 memory and registers 3 (1) the por bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. table 3-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected
mc68hc05b6 motorola 3-9 memory and registers 3 3.8 miscellaneous register por power-on reset bit (see section 9.1) this bit is set each time the de vice is powered on. therefore , the state of the por bit allo ws the user to make a software distinction between a power-on and an exter nal reset. this bit cannot be set by software and is cleared by writing it to zero. 1 (set) C a power-on reset has occurred. 0 (clear) C no power-on reset has occurred. intp, intn external interrupt sensitivity options (see section 9.2) these tw o bits allo w the user to select which edge the irq pin will be sensitiv e to (see t able 3-3). both bits can be wr itten to only while the i-bit is set, and are cleared b y pow er-on or e xternal reset, thus the device is initialised with negative edge and low level sensitivity. inte external interrupt enable (see section 9.2) 1 (set) C external interrupt function ( irq) enabled. 0 (clear) C external interrupt function ( irq) disabled. the inte bit can be written to only while the i-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. (1) the por bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? table 3-3 irq sensitivity intp intn irq sensitivity 0 0 negative edge and low level sensitive 0 1 negative edge only 1 0 positive edge only 1 1 positive and negative edge sensitive
motorola 3-10 mc68hc05b6 memory and registers 3 sfa slow or fast mode selection for plma (see section 7.1) this bit allo ws the user to select the slo w or f ast mode of the plma pulse length modulation output. 1 (set) C slow mode plma (4096 x timer clock period). 0 (clear) C fast mode plma (256 x timer clock period). sfb slow or fast mode selection for plmb (see section 7.1) this bit allo ws the user to select the slo w or f ast mode of the plmb pulse length modulation output. 1 (set) C slow mode plmb (4096 x timer clock period). 0 (clear) C fast mode plmb (256 x timer clock period). note: the highest speed of the plm system corresponds to the frequency of the t of bit being set, multiplied by 256. the low est speed of the plm system corresponds to the frequency of the tof bit being set, multiplied by 16. warning: because the sf a bit and sfb bit are not doub le buff ered, it is mandator y to set the sf a bit and sfb bit to the desired v alues before wr iting to the plm registers; not doing so could temporarily give incorrect values at the plm outputs. sm slow mode (see section 2.4.3) 1 (set) C the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sections of the device, including sci, a/d and timer. 0 (clear) C the system runs at normal bus speed (f osc /2). the sm bit is cleared by external or power-on reset. the sm bit is automatically cleared when entering stop mode. wdog watchdog enable/disable (see section 9.1.4) the wdog bit can be used to enab le the watchdog timer previously disabled b y a mask option. following a w atchdog reset the state of the wdog bit is as de?ned b y the mask option speci?ed. 1 (set) C watchdog counter cleared and enabled. 0 (clear) C the watchdog cannot be disabled by software; writing a zero to this bit has no effect.
mc68hc05b6 motorola 4-1 input/output ports 4 4 input/output ports in single-chip mode , the mc68hc05b6 has a total of 24 i/o lines , arr anged as three 8-bit por ts (a, b and c), and eight input-only lines , arr anged as one 8-bit por t (d). each i/o line is individually programmab le as either input or output, under the softw are control of the data direction registers . the 8-bit input-only por t (d) shares its pins with the a/d con verter , when the a/d con ver ter is enabled. to av oid glitches on the output pins , data should be wr itten to the i/o por t data register before wr iting ones to the corresponding data direction register bits to set the pins to output mode . 4.1 input/output programming the bidirectional port lines may be programmed as inputs or outputs under software control. the direction of each pin is determined by the state of the corresponding bit in the port data direction register (ddr). each por t has an associated ddr. an y i/o por t pin is con?gured as an output if its corresponding ddr bit is set to a logic one . a pin is con?gured as an input if its corresponding ddr bit is cleared to a logic zero. at po w er-on or reset, all ddrs are cleared, thus con?gur ing all por t pins as inputs . the data direction registers can be wr itten to or read b y the mcu. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. the operation of the standard port hardware is shown schematically in figure 4-1.
motorola 4-2 mc68hc05b6 input/output ports 4 table 4-1 shows the effect of reading from or writing to an i/o pin in various circumstances. note that the read/write signal shown is internal and not available to the user. 4.2 ports a and b these por ts are standard m68hc05 bidirectional i/o por ts, each compr ising a data register and a data direction register. reset does not aff ect the state of the data register , but clears the data direction register, thereby returning all port pins to input mode. writing a 1 to an y ddr bit sets the corresponding por t pin to output mode. figure 4-1 standard i/o port structure table 4-1 i/o pin states r/ w ddrn action of mcu write to/read of data bit 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch, and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. latched data register bit ddrn data input buffer output buffer o/p data buffer m68hc05 internal connections ddrn data i/o pin 1 0 0 1 1 1 0 0 tristate 0 1 tristate i/o pin output ? input data direction register bit ?
mc68hc05b6 motorola 4-3 input/output ports 4 4.3 port c in addition to the standard por t functions descr ibed f or por t a and b , por t c pin 2 can be con?gured, using the eclk bit of the eepr om/eclk control register , to output the cpu cloc k. if this is selected the corresponding ddr bit is automatically set and bit 2 of por t c will always read the output data latch. the other port c pins are not affected by this feature. eclk external clock output bit 1 (set) C eclk cpu clock is output on pc2. 0 (clear) C eclk cpu cloc k is not output on pc2; por t c acts as a nor mal i/o por t. the eclk bit is cleared b y po w er-on or e xter nal reset. it is not aff ected b y the e x ecution of a st op or wait instruction. the timing diagram of the clock output is shown in figure 4-2. 4.4 port d this 8-bit input-only por t shares its pins with the a/d con ver ter subsystem. when the a/d converter is enab led, pins pd0-pd7 read the eight analog inputs to the a/d con verter. port d can be read at an y time , ho wever , if it is read dur ing an a/d con v ersion sequence noise , ma y be injected on the analog inputs, resulting in reduced accuracy of the a/d. furthermore, performing address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 figure 4-2 eclk timing diagram internal clock (phi2) external clock (eclk/pc2) output port (if write to output port)
motorola 4-4 mc68hc05b6 input/output ports 4 a digital read of por t d with le v els other than v dd or v ss on the por t d pins will result in g reater power dissipation during the read cycle. as por t d is an input-only por t there is no ddr associated with it. also , at po w er up or e xternal reset, the a/d converter is disabled, thus the port is con?gured as a standard input-only port. note: it is recommended that all un used input por ts and i/o por ts be tied to an appropr iate logic level (i.e. either v dd or v ss ). 4.5 port registers the f ollo wing sections e xplain in detail the individual bits in the data and control registers associated with the ports. 4.5.1 port data registers a and b (porta and portb) each bit can be con?gured as input or output via the corresponding data direction bit in the por t data direction register (ddrx). the state of the port data registers following reset is not de?ned. 4.5.2 port data register c (portc) each bit can be con?gured as input or output via the corresponding data direction bit in the por t data direction register (ddrx). in addition, bit 2 of por t c is used to output the cpu cloc k if the eclk bit in the eepr om ctl/eclk register is set (see section 4.3). the state of the port data registers following reset is not de?ned. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port c data (portc) $0002 pc2/ eclk unde?ned
mc68hc05b6 motorola 4-5 input/output ports 4 4.5.3 port data register d (portd) all the por t d bits are input-only and are shared with the a/d con verter . the function of each bit is determined by the adon bit in the a/d status/control register. the state of the port data registers following reset is not de?ned. 4.5.3.1 a/d status/control register adon a/d converter on 1 (set) C a/d converter is s witched on; all por t d pins act as analog inputs f or the a/d converter. 0 (clear) C a/d converter is switched off; all port d pins act as input only pins. reset clears the adon bit, thus con?guring port d as an input only port. 4.5.4 data direction registers (ddra, ddrb and ddrc) writing a 1 to an y bit con?gures the corresponding por t pin as an output; con versely, writing any bit to 0 con?gures the corresponding port pin as an input. reset clears these registers, thus con?guring all ports as inputs. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000
motorola 4-6 mc68hc05b6 input/output ports 4 4.6 other port considerations all output por ts can em ulate open-drain outputs . this is achie ved by wr iting a z ero to the rele vant output por t latch. by toggling the corresponding data direction bit, the por t pin will either be an output zero or tri-state (an input). this is shown diagrammatically in figure 4-3. when using a por t pin as an open-dr ain output, cer tain precautions m ust be tak en in the user software . if a read-modify-wr ite instr uction is used on a por t where the open-dr ain is assigned and the pin at this time is prog r ammed as an input, it will read it as a one. the read-modify-wr ite instruction will then wr ite this one into the output data latch on the ne xt cycle. this would cause the open-drain pin not to output a zero when desired. note: open-drain outputs should not be pulled above v dd . figure 4-3 port logic levels ddrn a y (b) 1 0 0 normal operation C tri state 1 1 1 0 0 tri state 0 1 tri state 1 0 low open-drain 1 1 0 0 high 0 1 high y t ? ? y t ? ? y a read buffer output data direction register bit ddrn px0 vdd v dd ddrx, bit 0 = 0 portx, bit 0 = 0 ddrx, bit 0 = 0 portx, bit 0 = 0 (c) (a) open-drain output
mc68hc05b6 motorola 5-1 programmable timer 5 5 programmable timer the prog rammab le timer on the mc68hc05b6 consists of a 16-bit read-only free-r unning counter , with a ?x ed divide-b y-f our prescaler , plus the input capture/output compare circuitr y . the timer can be used for many purposes including measuring pulse length of two input signals and generating tw o output signals . pulse lengths f or both input and output signals can v ar y from se veral microseconds to man y seconds . in addition, it w or ks in conjunction with the pulse width modulation (plm) system to e x ecute tw o 8-bit d/a plm (pulse length modulation) con versions, with a choice of tw o repetition rates . the timer is also capab le of generating periodic interrupts or indicating passage of an arbitr ary m ultiple of f our cpu cycles . a b lock diagr am is sho wn in figure 5-1, and timing diagrams are shown in figure 5-2, figure 5-3, figure 5-4 and figure 5-5. the timer has a 16-bit architecture , hence each speci?c functional segment is represented b y two 8-bit registers (e xcept the plma and plmb which use one 8-bit register f or each). these registers contain the high and lo w b yte of that functional segment. accessing the lo w b yte of a speci?c timer function allo ws full control of that function; ho wever , an access of the high b yte inhibits that speci?c timer function until the low byte is also accessed. the 16-bit prog rammab le timer is monitored and controlled b y a g roup of sixteen registers , full details of which are contained in this section. note: a prob lem ma y ar ise if an interr upt occurs in the time betw een the high and lo w b ytes being accessed. t o prev ent this , the i-bit in the condition code register (ccr) should be set while manipulating both the high and lo w b yte register of a speci?c timer function, ensuring that an interrupt does not occur. 5.1 counter the ke y element in the prog rammab le timer is a 16-bit, free-r unning counter or counter register , preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2 s if the internal bus cloc k is 2 mhz. the counter is incremented dur ing the low por tion of the inter nal bus clock. softw are can read the counter at an y time without aff ecting its value.
motorola 5-2 mc68hc05b6 programmable timer 5 figure 5-1 16-bit programmable timer block diagram internal internal bus 8 output compare register 1 processor clock + + 8-bit buffer 4 high low 16-bit free-running counter counter alternate register register 1 register 2 input capture internal timer bus over?ow detect circuit edge detect tcap1 tcmp2 tcmp1 latch d c q compare output register 2 input capture byte byte high byte low byte high byte low byte high byte low byte low byte high byte circuit 1 compare output circuit 2 compare output circuit 1 edge detect circuit 2 tcap2 pin pin pin pin d c q latch 7 6 5 4 3 timer status register timer control $0013 $0012 $0018 $0019 $001a $001b $001c $0016 $0017 $0014 $0015 $001e $001f $001d to plm register icf1 ocf1 tof icf2 ocf2 icie ocie toie folv2 olvl2 iedg1 olvl1 folv1 interrupt circuit input capture interrupt $1ff8,9 output compare interrupt $1ff6,7 over?ow interrupt $1ff4,5 cop watchdog counter input
mc68hc05b6 motorola 5-3 programmable timer 5 5.1.1 counter register and alternate counter register the double-byte, free-r unning counter can be read from either of tw o locations, $18-$19 (counter register) or $1a-$1b (alter nate counter register). a read from only the less signi?cant b yte (lsb) of the free-r unning counter ($19 or $1b) receiv es the count v alue at the time of the read. if a read of the free-r unning counter or alter nate counter register ?rst addresses the more signi?cant b yte (msb) ($18 or $1a), the lsb is tr ansf erred to a b uffer . this b uffer v alue remains ?x ed after the ?rst msb read, e v en if the user reads the msb se veral times . this b uff er is accessed when reading the free-r unning counter or alter nate counter register lsb and thus completes a read sequence of the total counter value. in reading either the free-running counter or alternate counter register, if the msb is read, the lsb m ust also be read to complete the sequence . if the timer o ver?ow ?ag (t of) is set when the counter register lsb is read then a read of the timer status register (tsr) will clear the ?ag. the alter nate counter register diff ers from the counter register only in that a read of the lsb does not clear t of . theref ore , where it is cr itical to a v oid the possibility of missing timer o ver?ow interrupts due to clearing of tof, the alternate counter register should be used. the free-r unning counter is set to $fffc dur ing po w er-on and e xter nal reset and is alw a ys a read-only register . dur ing a po w er-on reset, the counter begins r unning after the oscillator star t-up delay. because the free-r unning counter is 16 bits preceded b y a ?xed divide-by-4 prescaler, the v alue in the free-r unning counter repeats e ver y 262,144 inter nal b us cloc k cycles . t of is set when the counter over?ows (from $ffff to $0000); this will cause an interrupt if toie is set. in some par ticular timing control applications it ma y be desir ab le to reset the 16-bit free r unning counter under softw are control. when the lo w b yte of the counter ($19 or $1b) is wr itten to, the counter is con?gured to its reset value ($fffc). the divide-b y-4 prescaler is also reset and the counter resumes nor mal counting operation. all of the ?ags and enable bits remain unaltered by this operation. if access has previously been made to the high b yte of the free-r unning counter ($18 or $1a), then the reset counter oper ation terminates the access sequence. warning: this operation may aff ect the function of the w atchdog system (see section 9.1.4). the plm results will also be affected while resetting the counter. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100
motorola 5-4 mc68hc05b6 programmable timer 5 5.2 timer control and status the var ious functions of the timer are monitored and controlled using the timer control and status registers described below. 5.2.1 timer control register (tcr) the timer control register ($0012) is used to enab le the input captures (icie), output compares (ocie), and timer o ver?o w (t oie) functions as w ell as f orcing output compares (fol v1 and folv2), selecting input edge sensitivity (iedg1) and levels of output polarity (olv1 and olv2). icie input captures interrupt enable if this bit is set, a timer interr upt is enab led whene v er the icf1 or icf2 status ?ag (in the timer status register) is set. 1 (set) C interrupt enabled. 0 (clear) C interrupt disabled. ocie output compares interrupt enable if this bit is set, a timer interr upt is enabled whenev er the ocf1 or ocf2 status ?ag (in the timer status register) is set. 1 (set) C interrupt enabled. 0 (clear) C interrupt disabled. toie timer over?ow interrupt enable if this bit is set, a timer interr upt is enab led whene v er the t of status ?ag (in the timer status register) is set. 1 (set) C interrupt enabled. 0 (clear) C interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0
mc68hc05b6 motorola 5-5 programmable timer 5 folv2 force output compare 2 this bit alw a ys reads as z ero , hence wr iting a z ero to this bit has no eff ect. wr iting a one at this position will f orce the ol v2 bit to the corresponding output le v el latch, thus appear ing at the tcmp2 pin. note that this bit does not aff ect the ocf2 bit of the status register (see section 5.4.3). 1 (set) C olv2 bit forced to output level latch. 0 (clear) C no effect. folv1 force output compare 1 this bit alw a ys reads as z ero , hence wr iting a z ero to this bit has no eff ect. wr iting a one at this position will f orce the ol v1 bit to the corresponding output le v el latch, thus appear ing at the tcmp1 pin. note that this bit does not aff ect the ocf1 bit of the status register (see section 5.4.3). 1 (set) C olv1 bit forced to output level latch. 0 (clear) C no effect. olv2 output level 2 when ol v2 is set a high output le v el will be cloc k ed into the output le v el register b y the ne xt successful output compare , and will appear on the tcmp2 pin. when clear , it will be a lo w level which will appear on the tcmp2 pin. 1 (set) C a high output level will appear on the tcmp2 pin. 0 (clear) C a low output level will appear on the tcmp2 pin. iedg1 input edge 1 when iedg1 is set, a positiv e-going edge on the tcap1 pin will tr igger a tr ansf er of the free-r unning counter v alue to the input capture register 1. when clear , a negativ e-going edge triggers the transfer. 1 (set) C tcap1 is positive-going edge sensitive. 0 (clear) C tcap1 is negative-going edge sensitive. note: there is no need f or an equiv alent bit f or the input capture register 2 as tcap2 is negative-going edge sensitive only. olv1 output level 1 when ol v1 is set a high output le v el will be cloc k ed into the output le v el register b y the ne xt successful output compare , and will appear on the tcmp1 pin. when clear , it will be a lo w level which will appear on the tcmp1 pin. 1 (set) C a high output level will appear on the tcmp1 pin. 0 (clear) C a low output level will appear on the tcmp1 pin.
motorola 5-6 mc68hc05b6 programmable timer 5 5.2.2 timer status register (tsr) the timer status register ($13) contains the status bits corresponding to the f our timer interr upt conditions C icf1,ocf1, tof, icf2 and ocf2. accessing the timer status register satis?es the ?rst condition required to clear the status bits . the remaining step is to access the register corresponding to the status bit. icf1 input capture ?ag 1 this bit is set when the selected polar ity of edge is detected by the input capture edge detector 1 at tcap1; an input capture interr upt will be gener ated, if icie is set. icf1 is cleared b y reading the tsr and then the input capture low register 1 ($15). 1 (set) C a valid input capture has occurred. 0 (clear) C no input capture has occurred. ocf1 output compare ?ag 1 this bit is set when the output compare 1 register contents match those of the free-r unning counter ; an output compare interr upt will be gener ated if ocie is set. ocf1 is cleared b y reading the tsr and then the output compare 1 low register ($17). 1 (set) C a valid output compare has occurred. 0 (clear) C no output compare has occurred. tof timer over?ow status ?ag this bit is set when the free-r unning counter o v er?o ws from $ffff to $0000; a timer o v er?o w interr upt will occur if t oie is set. t of is cleared b y reading the tsr and the counter lo w register ($19). 1 (set) C timer over?ow has occurred. 0 (clear) C no timer over?ow has occurred. when using the timer o ver?o w function and reading the free-r unning counter at r andom times to measure an elapsed time, a problem may occur whereby the timer over?ow ?ag is unintentionally cleared if: 1 the timer status register is read or written when tof is set, and 2 the lsb of the free-running counter is read, but not for the purpose of servicing the ?ag. reading the alter nate counter register instead of the counter register will a v oid this potential problem. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned
mc68hc05b6 motorola 5-7 programmable timer 5 icf2 input capture ?ag 2 this bit is set when a negativ e edge is detected b y the input capture edge detector 2 at tcap2; an input capture interrupt will be gener ated if icie is set. icf2 is cleared b y reading the tsr and then the input capture low register 2 ($1d). 1 (set) C a valid (negative) input capture has occurred. 0 (clear) C no input capture has occurred. ocf2 output compare ?ag 2 this bit is set when the output compare 2 register contents match those of the free-r unning counter ; an output compare interr upt will be gener ated if ocie is set. ocf2 is cleared b y reading the tsr and then the output compare 2 low register ($1f). 1 (set) C a valid output compare has occurred. 0 (clear) C no output compare has occurred. 5.3 input capture input capture is a technique whereb y an e xter nal signal is used to tr igger a read of the free running counter . in this w a y it is possib le to relate the timing of an e xter nal signal to the inter nal counter value, and hence to elapsed time. there are tw o input capture registers: input capture register 1 (icr1) and input capture register 2 (icr2). the same input capture interrupt enable bit (icie) is used for the two input captures. 5.3.1 input capture register 1 (icr1) the tw o 8-bit registers that mak e up the 16-bit input capture register 1 are read-only , and are used to latch the v alue of the free-r unning counter after the input capture edge detector circuit 1 senses a valid transition at tcap1. the level transition that triggers the counter transfer is de?ned by the input edge bit (iedg1). when an input capture 1 occurs , the corresponding ?ag icf1 in tsr is set. an interrupt can also accompany an input capture 1 pro vided the icie bit in tcr is set. the 8 most signi?cant bits are stored in the input capture high 1 register at $14, the 8 least signi?cant bits in the input capture low 1 register at $15. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned
motorola 5-8 mc68hc05b6 programmable timer 5 the result obtained from an input capture will be one g reater than the v alue of the free-r unning counter on the r ising edge of the inter nal bus cloc k preceding the e xternal transition. this delay is required for inter nal synchronization. resolution is one count of the free-r unning counter , which is f our inter nal b us cloc k cycles . the free-r unning counter contents are tr ansf erred to the input capture register 1 on each v alid signal tr ansition whether the input capture 1 ?ag (icf1) is set or clear . the input capture register 1 alw a ys contains the free-r unning counter v alue that corresponds to the most recent input capture 1. after a read of the input capture 1 register msb ($14), the counter transfer is inhibited until the lsb ($15) is also read. this characteristic causes the time used in the input capture softw are routine and its inter action with the main prog r am to deter mine the minim um pulse per iod. a read of the input capture 1 register lsb ($15) does not inhibit the free-r unning counter tr ansf er since the tw o actions occur on opposite edges of the internal bus clock. reset does not aff ect the contents of the input capture 1 register , e xcept when e xiting st op mode (see section 5.6). 5.3.2 input capture register 2 (icr2) the tw o 8-bit registers that mak e up the 16-bit input capture register 2 are read-only , and are used to latch the v alue of the free-r unning counter after the input capture edge detector circuit 2 senses a negative tr ansition at pin tcap2. when an input capture 2 occurs , the corresponding ?ag icf2 in tsr is set. an interr upt can also accompan y an input capture 2 pro vided the icie bit in tcr is set.the 8 most signi?cant bits are stored in the input capture 2 high register at $1c , the 8 least signi?cant bits in the input capture 2 low register at $1d. the result obtained from an input capture will be one g reater than the v alue of the free-r unning counter on the r ising edge of the inter nal bus cloc k preceding the e xternal transition. this delay is required for inter nal synchronization. resolution is one count of the free-r unning counter , which is f our inter nal b us cloc k cycles . the free-r unning counter contents are tr ansf erred to the input capture register 2 on each negativ e signal tr ansition whether the input capture 2 ?ag (ic2f) is set or clear . the input capture register 2 alw a ys contains the free-r unning counter v alue that corresponds to the most recent input capture 2. after a read of the input capture register 2 msb ($1c), the counter tr ansf er is inhibited until the lsb ($1d) is also read. this char acteristic causes the time used in the input capture softw are routine and its inter action with the main prog r am to deter mine the minim um pulse per iod. a read of the input capture register 2 lsb ($1c) does not inhibit the free-r unning counter tr ansf er since the tw o actions occur on opposite edges of the internal bus clock. reset does not aff ect the contents of the input capture 2 register , e xcept when e xiting st op mode (see section 5.6). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned
mc68hc05b6 motorola 5-9 programmable timer 5 5.4 output compare output compare is a technique which ma y be used, f or e xample , to gener ate an output w aveform, or to signal when a speci?c time per iod has elapsed, b y presetting the output compare register to the appropriate value. there are tw o output compare registers: output compare register 1 (ocr1) and output compare register 2 (ocr2). note: the same output compare interr upt enab le bit (ocie) is used f or the tw o output compares. 5.4.1 output compare register 1 (ocr1) the 16-bit output compare register 1 is made up of tw o 8-bit registers at locations $16 (msb) and $17 (lsb). the contents of the output compare register 1 are compared with the contents of the free-running counter contin ually and, if a match is f ound, the corresponding output compare ?ag (ocf1) in the timer status register is set and the output le vel (ol vl1) is tr ansf erred to pin tcmp1. the output compare register 1 v alues and the output le v el bit should be changed after each successful compar ison to estab lish a ne w elapsed timeout. an interr upt can also accompan y a successful output compare pro vided the corresponding interr upt enab le bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor wr ite cycle to the output compare register 1 containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also wr itten. the user m ust wr ite both b ytes (locations) if the msb is wr itten ?rst. a wr ite made only to the lsb ($17) will not inhibit the compare 1 function. the processor can wr ite to either b yte of the output compare register 1 without aff ecting the other b yte . the output le vel (ol vl1) bit is cloc k ed to the output le v el register and hence to the tcmp1 pin whether the output compare ?ag 1 (ocf1) is set or clear . the minimum time required to update the output compare register 1 is a function of the prog r am r ather than the inter nal hardware . because the output compare ?ag 1 and the output compare register 1 are not de?ned at po w er on, and not aff ected b y reset, care m ust be tak en when initializing output compare functions with software. the following procedure is recommended: C write to output compare high 1 to inhibit further compares; C read the timer status register to clear ocf1 (if set); C write to output compare low 1 to enable the output compare 1 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned
motorola 5-10 mc68hc05b6 programmable timer 5 the pur pose of this procedure is to pre v ent the ocf1 bit from being set betw een the time it is read and the write to the corresponding output compare register. all bits of the output compare register are readab le and writab le and are not altered b y the timer hardw are or reset. if the compare function is not needed, the tw o b ytes of the output compare register can be used as storage locations. 5.4.2 output compare register 2 (ocr2) the 16-bit output compare register 2 is made up of tw o 8-bit registers at locations $1e (msb) and $1f (lsb). the contents of the output compare register 2 are compared with the contents of the free-running counter contin ually and, if a match is f ound, the corresponding output compare ?ag (ocf2) in the timer status register is set and the output le vel (ol vl2) is tr ansf erred to pin tcmp2. the output compare register 2 v alues and the output le v el bit should be changed after each successful compar ison to estab lish a ne w elapsed timeout. an interr upt can also accompan y a successful output compare pro vided the corresponding interr upt enab le bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor wr ite cycle to the output compare register 2 containing the msb ($1e), the output compare function is inhibited until the lsb ($1f) is also wr itten. the user must write both b ytes (locations) if the msb is wr itten ?rst. a wr ite made only to the lsb ($1f) will not inhibit the compare 2 function. the processor can wr ite to either b yte of the output compare register 2 without affecting the other byte. the output level (olvl2) bit is clock ed to the output le vel register and hence to the tcmp2 pin whether the output compare ?ag 2 (ocf2) is set or clear . the minim um time required to update the output compare register 2 is a function of the prog ram rather than the inter nal hardware . because the output compare ?ag 2 and the output compare register 2 are not de?ned at po w er on, and not aff ected b y reset, care m ust be tak en when initializing output compare functions with software. the following procedure is recommended: C write to output compare high 2 to inhibit further compares; C read the timer status register to clear ocf2 (if set); C write to output compare low 2 to enable the output compare 2 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned
mc68hc05b6 motorola 5-11 programmable timer 5 the pur pose of this procedure is to pre v ent the ocf1 bit from being set betw een the time it is read and the write to the corresponding output compare register. all bits of the output compare register are readab le and writab le and are not altered b y the timer hardw are or reset. if the compare function is not needed, the tw o b ytes of the output compare register can be used as storage locations. 5.4.3 software force compare a softw are f orce compare is required in man y applications . t o achie v e this , bit 3 (fol v1 f or ocr1) and bit 4 (fol v2 f or ocr2) in the timer control register are used. these bits alw a ys read as z ero, but a wr ite to one causes the respectiv e olvl1 or olvl2 v alues to be copied to the respectiv e output level (tcmp1 and tcmp2 pins). internal logic is arranged such that in a single instruction, one can change olvl1 and/or olvl2, at the same time causing a f orced output compare with the ne w values of olvl1 and olvl2. in conjunction with normal compare , this function allo ws a wide r ange of applications including ?x ed frequency generation. note: a softw are f orce compare will aff ect the corresponding output pin tcmp1 and/or tcmp2, but will not affect the compare ?ag, thus it will not generate an interrupt. 5.5 pulse length modulation (plm) the programmable timer wor ks in conjunction with the plm system to e xecute tw o 8-bit d/a plm conversions, with a choice of two repetition rates (see section 7). 5.5.1 pulse length modulation register s a and b (plma/plmb) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation a (plma) $000a 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation b (plmb) $000b 0000 0000
motorola 5-12 mc68hc05b6 programmable timer 5 5.6 timer during stop mode when the mcu enters st op mode , the timer counter stops counting and remains at that par ticular count v alue until st op mode is e xited b y an interr upt. if st op mode is e xited b y pow er-on or e xter nal reset, the counter is f orced to $fffc b ut if it is e xited by external interrupt ( irq) then the counter resumes from its stopped value. another f eature of the prog rammab le timer is that if at least one v alid input capture edge occurs at one of the tcap pins while in st op mode , the corresponding input capture detect circuitr y is ar med. this action does not w ak e the mcu or set an y timer ?ags , b ut when the mcu does wak e-up there will be an activ e input capture ?ag (and data) from that ?rst v alid edge which occurred during stop mode. if st op mode is e xited by an exter nal reset then no such input capture ?ag or data action tak es place even if there was a valid input capture edge (at one of the tcap pins) during stop mode. 5.7 timer during wait mode the timer system is not aff ected by wait mode and continues normal operation. any valid timer interrupt will wake-up the system. 5.8 timer state diagrams the relationships betw een the inter nal clock signals , the counter contents and the status of the ?ag bits are sho wn in the f ollowing ?gures . it should be noted that the signals labelled inter nal (processor clock, timer clocks and reset) are not available to the user.
mc68hc05b6 motorola 5-13 programmable timer 5 figure 5-2 timer state timing diagram for reset figure 5-3 timer state timing diagram for input capture internal processor clock internal reset 16-bit counter external reset or end of por internal timer clocks ? ? ? $fffc $fffd $fffe $ffff note: the counter and timer control registers are the only ones affected by power-on or external reset. t00 t01 t11 t10 internal processor clock 16-bit counter $f123 $f124 $f125 $f126 internal timer clocks ? ? ? t00 t01 t11 t10 internal capture latch $f124 $???? input capture register input capture ?ag input edge } } } } note: if the input edge occurs in the shaded area from one timer state t10 to the ne xt timer state t10, then the input capture ?ag will be set during the next t11 state.
motorola 5-14 mc68hc05b6 programmable timer 5 figure 5-4 timer state timing diagram for output compare figure 5-5 timer state timing diagram for timer over?ow internal processor clock 16-bit counter $f456 $f457 $f458 $f459 internal timer clocks ? ? ? t00 t01 t11 t10 $f457 cpu writes $f457 output compare ?ag and tcmp1,2 note: 1 the cpu write to the compare registers may take place at any time, but a compare only occurs at timer state t01. thus a f our cycle diff erence may exist betw een the wr ite to the compare register and the actual compare . 2 the output compare ?ag is set at the timer state t11 that f ollo ws the compar ison match ($f457 in this e xample). output compare register compare register latch (note 2) (note 1) (note 1) internal processor clock 16-bit counter $ffff $0000 $0001 $0002 internal timer clocks ? ? ? t00 t01 t11 t10 note: the timer over?o w ?ag is set at timer state t11 (tr ansition of counter from $ffff to $0000). it is cleared b y a read of the timer status register dur ing the inter nal processor cloc k high time , followed b y a read of the counter low register. timer over?ow ?ag
mc68hc05b6 motorola 6-1 serial communications interface 6 6 serial communications interface a full-duple x asynchronous ser ial comm unications interf ace (sci) is pro vided with a standard non-return-to-z ero (nrz) f or mat and a v ar iety of baud r ates . the sci tr ansmitter and receiv er are functionally independent and have their own baud rate generator; however they share a common baud rate prescaler and data format. the ser ial data f or mat is standard mar k/space (nrz) and pro vides one star t bit, eight or nine data bits, and one stop bit. the sclk pin is the output of the tr ansmitter cloc k. it outputs the tr ansmitter data cloc k f or synchronous transmission (no clocks on star t bit and stop bit, and a softw are option to send cloc k on last data bit). this allo ws control of per ipher als containing shift registers (e .g. lcd dr ivers). phase and polarity of these clocks are software programmable. an y sci bidirectional comm unication requires a tw o-wire system: receiv e data in (rdi) and transmit data out (tdo). baud and bit rate are used synonymously in the following description. 6.1 sci two-wire system features ? standard nrz (mark/space) format ? adv anced error detection method with noise detection f or noise dur ation of up to 1/16th bit time ? full-duplex operation (simultaneous transmit and receive) ? 32 software selectable baud rates ? different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive baud rates ? software selectable word length (eight or nine bits) ? separate transmitter and receiver enable bits ? capable of being interrupt driven ? transmitter clocks available without altering the regular transmitter or receiver functions ? four separate enable bits for interrupt control
motorola 6-2 mc68hc05b6 serial communications interface 6 figure 6-1 serial communications interface block diagram & & & & + + internal bus sci interrupt transmit receive tdo pin rdi transmitter control receiver control clock clock extraction phase and polarity control pin receiver clock transmitter flag control data register data register tie tcie rie ilie te re sbk rwu 7 6 5 4 3 2 1 0 $000f sccr2 scsr $0010 sccr1 $000e trde tc rdrf idle or nf fe te sbk $0011 (see note) (see note) r8 t8 m wake cpol cpha lbcl 0 1 2 4 3 6 5 7 7 6 5 2 3 4 1 sclk pin wake up unit receive data shift register transmit data shift register $0011 note: the serial communications data register (sci scdr) is controlled by the internal r/ w signal. it is the tr ansmit data register when wr itten to and the receiv e data register when read. 7
mc68hc05b6 motorola 6-3 serial communications interface 6 6.2 sci receiver features ? receiver wake-up function (idle line or address bit) ? idle line detection ? framing error detection ? noise detection ? overrun detection ? receiver data register full ?ag 6.3 sci transmitter features ? transmit data register empty ?ag ? transmit complete ?ag ? send break 6.4 functional description a block diagr am of the sci is sho wn in figure 6-1. option bits in ser ial control register1 (sccr1) select the w ak e-up method (w ake bit) and data w ord length (m-bit) of the sci. sccr2 pro vides control bits that individually enab le the tr ansmitter and receiv er , enab le system interr upts and pro vide the w ake-up enab le bit (r wu) and the send break code bit (sbk). control bits in the baud rate register (baud) allo w the user to select one of 32 diff erent baud rates for the transmitter and receiver (see section 6.11.5). data tr ansmission is initiated b y wr iting to the ser ial comm unications data register (scdr). pro vided the tr ansmitter is enab led, data stored in the scdr is tr ansf erred to the tr ansmit data shift register . this tr ansf er of data sets the tr ansmit data register empty ?ag (tdre) in the sci status register (scsr) and gener ates an interr upt (if tr ansmitter interr upts are enab led). the transf er of data to the tr ansmit data shift register is synchroniz ed with the bit r ate clock (see figure 6-2). all data is tr ansmitted least signi?cant bit ?rst. upon completion of data tr ansmission, the tr ansmission complete ?ag (tc) in the scsr is set (pro vided no pending data, preamb le or break is to be sent) and an interr upt is gener ated (if the tr ansmit complete interr upt is enab led). if the tr ansmitter is disab led, and the data, preamb le or break (in the tr ansmit data shift register) has been sent, the tc bit will also be set. this will also gener ate an interr upt if the tr ansmission complete interrupt enab le bit (tcie) is set. if the tr ansmitter is disab led dur ing a tr ansmission, the char acter being tr ansmitted will be completed bef ore the tr ansmitter giv es up control of the tdo pin.
motorola 6-4 mc68hc05b6 serial communications interface 6 when scdr is read, it contains the last data b yte received, pro vided that the receiv er is enabled. the receiv e data register full ?ag bit (rdrf) in the scsr is set to indicate that a data b yte has been transferred from the input serial shift register to the scdr; this will cause an interrupt if the receiver interrupt is enab led. the data tr ansf er from the input ser ial shift register to the scdr is synchronized b y the receiv er bit r ate cloc k. the or (o verr un), nf (noise), or fe (fr aming) error ?ags in the scsr may be set if data reception errors occurred. an idle line interr upt is gener ated if the idle line interr upt is enab led and the idle bit (which detects idle line tr ansmission) in scsr is set. this allo ws a receiv er that is not in the w ak e-up mode to detect the end of a message or the preamb le of a ne w message , or to resynchroniz e with the transmitter . a v alid character m ust be receiv ed bef ore the idle line condition or the idle bit will not be set and idle line interrupt will not be generated. the scp0 and scp1 bits function as a prescaler f or scr0Cscr2 to gener ate the receiv er baud r ate and f or sct0Csct2 to gener ate the tr ansmitter baud r ate . t ogether , these eight bits pro vide m ultiple tr ansmitter/receiv er r ate combinations f or a giv en cr ystal frequency (see figure 6-2). this register should only be wr itten to while both the tr ansmitter and receiv er are disab led (te=0, re=0). figure 6-2 sci rate generator division scp1 spc0 sct2 sct1 sct0 scr2 scr1 scr0 internal processor clock scp0 C scp1 prescaler rate control ( np) scr0 C scr2 receiver ( nr) sct0 C sct2 transmitter rate control ( nt) 16 transmitter clock receiver clock rate control 7 6 5 4 3 2 1 0 $000d baud rate register note: there is a ?xed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling). this means that b y loading the same v alue f or both the tr ansmitter and receiver baud rate selector , the same baud r ates can be obtained.
mc68hc05b6 motorola 6-5 serial communications interface 6 6.5 data format receiv e data or tr ansmit data is the ser ial data that is tr ansf erred to the inter nal data b us from the receiv e data input pin (rdi) or from the inter nal b us to the tr ansmit data output pin (tdo). the non-return-to-z ero (nrz) data f or mat sho wn in figure 6-3 is used and m ust meet the f ollowing criteria: C the idle line is brought to a logic one state pr ior to tr ansmission/reception of a character. C a start bit (logic zero) is used to indicate the start of a frame. C the data is transmitted and received least signi?cant bit ?rst. C a stop bit (logic one) is used to indicate the end of a fr ame . a fr ame consists of a start bit, a character of eight or nine data bits, and a stop bit. C a break is de?ned as the tr ansmission or reception of a lo w (logic z ero) f or at least one complete fr ame time (10 z eros f or 8-bit f or mat, 11 z eros f or 9-bit) . 6.6 receiver wake-up operation the receiv er logic hardw are also suppor ts a receiv er w ak e-up function which is intended f or systems ha ving more than one receiv er . with this function a tr ansmitting de vice directs messages to an individual receiv er or g roup of receiv ers b y passing addressing inf or mation as the initial b yte(s) of each message . the w ak e-up function allo ws receiv ers not addressed to remain in a dor mant state f or the remainder of the unw anted message . this eliminates an y further software ov erhead to ser vice the remaining char acters of the unw anted message and thus impro ves system performance. the receiver is placed in wake-up mode by setting the receiver wake-up bit (rwu) in the sccr2 register. while r wu is set, all of the receiv er related status ?ags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). note that the idle line detect function is inhibited while the r wu bit is set. although r wu may be cleared by a software wr ite to sccr2, it w ould be unusual to do so. normally r wu is set b y softw are and is cleared automatically in hardw are b y one of the tw o methods described below. figure 6-3 data format start stop control bit m selects 8 or 9 bit data start idle line 0 1 2 3 4 5 6 7 8 ? 0
motorola 6-6 mc68hc05b6 serial communications interface 6 6.6.1 idle line wake-up in idle line w ake-up mode , a dor mant receiver wak es up as soon as the rdi line becomes idle . idle is de?ned as a contin uous logic high le v el on the rdi line f or ten (or ele v en) full bit times . systems using this type of w ak e-up m ust pro vide at least one char acter time of idle betw een messages to w ak e up sleeping receiv ers , b ut m ust not allo w an y idle time betw een char acters within a message. 6.6.2 address mark wake-up in address mar k wake-up , the most signi?cant bit (msb) in a char acter is used to indicate whether it is an address (1) or data (0) char acter . sleeping receiv ers will w ak e up whene v er an address char acter is receiv ed. systems using this method f or w ak e-up w ould set the msb of the ?rst char acter of each message and lea v e it clear f or all other char acters in the message . idle periods ma y be present within messages and no idle time is required betw een messages f or this w ake-up method. 6.7 receive data in (rdi) receiv e data is the ser ial data that is applied through the input line and the sci to the inter nal bus. the receiv er circuitr y cloc ks the input at a r ate equal to 16 times the baud r ate . this time is ref erred to as the rt rate in figure 6-4 and as the receiver clock in figure 6-2. the receiver clock gener ator is controlled b y the baud r ate register , as sho wn in figure 6-1 and figure 6-2; however, the sci is synchronized by the start bit, independent of the transmitter. once a v alid star t bit is detected, the star t bit, each data bit and the stop bit are sampled three times at r t interv als 8 r t , 9 r t and 10 r t (1 r t is the position where the bit is e xpected to star t), as sho wn in figure 6-5. the v alue of the bit is deter mined by v oting logic which tak es the value of the majority of the samples . a noise ?ag is set when all three samples on a v alid start bit or data bit or the stop bit do not agree. 6.8 start bit detection when the input (idle) line is detected lo w , it is tested f or three more sample times (ref erred to as the star t edge v er i?cation samples in figure 6-4). if at least tw o of these three v eri?cation samples detect a logic zero, a valid star t bit has been detected, otherwise the line is assumed to be idle . a noise ?ag is set if one of the three v er i?cation samples detect a logic one , thus a v alid star t bit could be assumed with a set noise ?ag present.
mc68hc05b6 motorola 6-7 serial communications interface 6 if there has been a fr aming error without detection of a break (10 z eros f or 8 bit f or mat or 11 z eros f or 9 bit f or mat), the circuit contin ues to oper ate as if there actually w as a stop bit, and the star t edge will be placed ar ti?cially . the last bit receiv ed in the data shift register is in ver ted to a logic one, and the three logic one start quali?ers (shown in figure 6-4) are forced into the sample shift register during the interval when detection of a start bit is anticipated (see figure 6-6); therefore, the start bit will be accepted no sooner than it is anticipated. figure 6-4 sci examples of start bit sampling technique figure 6-5 sci sampling technique used on all bits 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1rt 2rt 3rt 5rt 7rt 4rt 6rt 8rt start quali?ers idle start edge veri?cation samples 16x internal sampling clock rt clock edges for all three examples noise start 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 start start noise rdi rdi rdi < < < samples present bit next bit previous bit 16rt 1rt 8rt 9rt 10rt 16rt 1rt rdi
motorola 6-8 mc68hc05b6 serial communications interface 6 if the receiv er detects that a break (rdrf = 1, fe = 1, receiv er data register = $0000) produced the framing error, the star t bit will not be ar ti?cially induced and the receiver must actually detect a logic one before the start bit can be recognised (see figure 6-7). 6.9 transmit data out (tdo) tr ansmit data is the ser ial data from the inter nal data b us that is applied through the sci to the output line . data f or mat is as discussed in section 6.5 and sho wn in figure 6-3. the tr ansmitter gener ates a bit time b y using a der ivativ e of the r t cloc k, thus producing a tr ansmission r ate equal to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the receiver and transmitter). figure 6-6 arti?cial start following a framing error figure 6-7 sci start bit following a break data expected stop data samples arti?cial edge start bit data rdi data expected stop data samples start edge start bit data rdi a) case 1: receive line low during arti?cial edge b) case 2: receive line high during expected start edge expected stop data samples detected as valid start edge start bit rdi break ? ? ? ? ? ? ? ? ? ? ? start quali?ers start edge veri?cation samples
mc68hc05b6 motorola 6-9 serial communications interface 6 6.10 sci synchronous transmission the sci tr ansmitter allo ws the user to control a one w a y synchronous ser ial tr ansmission. the sclk pin is the cloc k output of the sci tr ansmitter. no cloc ks are sent to that pin dur ing start bit and stop bit. depending on the state of the lbcl bit (bit 0 of sccr1), cloc ks will or will not be activated during the last valid data bit (address mar k). the cpol bit (bit 2 of sccr1) allo ws the user to select the cloc k polarity , and the cpha bit (bit 1 of sccr1) allo ws the user to select the phase of the external clock (see figure 6-8, figure 6-9 and figure 6-10). during idle, preamble and send break, the external sclk clock is not activated. these options allo w the user to ser ially control per ipher als which consist of shift registers , without losing an y functions of the sci tr ansmitter which can still talk to other sci receiv ers . these options do not affect the sci receiver which is independent of the transmitter. the sclk pin w or ks in conjunction with the tdo pin. when the sci tr ansmitter is disab led (te = 0), the sclk and tdo pins go to the high impedance state. note: the lbcl, cpol and cpha bits ha v e to be selected bef ore enab ling the tr ansmitter to ensure that the cloc ks function correctly . these bits should not be changed while the transmitter is enabled. figure 6-8 sci example of synchronous and asynchronous transmission rdi tdo sclk output port data out data in data in clock enable asynchronous mc68hc05b6 (e.g. modem) synchronous (e.g. shift register, display driver, etc.)
motorola 6-10 mc68hc05b6 serial communications interface 6 6.11 sci registers the sci system is con?gured and controlled b y ?v e registers: scdr, sccr1, sccr2, scsr, and baud. 6.11.1 serial communications data register (scdr) the scdr is controlled by the internal r/ w signal and performs tw o functions in the sci. it acts as the receiv e data register (rdr) when it is read and as the tr ansmit data register (tdr) when it is wr itten. figure 6-1 sho ws this register as tw o separ ate registers , rdr and tdr. the rdr pro vides the interf ace from the receiv e shift register to the inter nal data b us and the tdr pro vides the parallel interface from the internal data bus to the transmit shift register. the receiv e data register is a read-only register containing the last b yte of data received from the shift register f or the inter nal data b us . the rdr full bit (rdrf) in the ser ial communications status register is set to indicate that a b yte has been transferred from the input serial shift register to the scdr. the transfer is synchronized with the receiver bit rate clock (from the receiver control) as shown in figure 6-1. all data is received with the least signi?cant bit ?rst. the tr ansmit data register (tdr) is a wr ite-only register containing the ne xt b yte of data to be applied to the tr ansmit shift register from the inter nal data b us . as long as the tr ansmitter is enab led, data stored in the scdr is tr ansf erred to the tr ansmit shift register (after the current b yte in the shift register has been transmitted). the tr ansf er is synchroniz ed with the tr ansmitter bit r ate cloc k (from the tr ansmitter control) as shown in figure 6-1. all data is received with the least signi?cant bit ?rst. 6.11.2 serial communications control register 1 (sccr1) the sci control register 1 (sccr1) contains control bits related to the nine data bit char acter for mat, the receiv er w ak e-up f eature and the options to output the tr ansmitter cloc ks f or synchronous transmissions. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci data (scdr) $0011 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned
mc68hc05b6 motorola 6-11 serial communications interface 6 r8 receive data bit 8 this read-only bit is the ninth ser ial data bit receiv ed when the sci system is con?gured f or nine data bit oper ation (m = 1). the most signi?cant bit (bit 8) of the receiv ed character is transferred into this bit at the same time as the remaining eight bits (bits 0C7) are tr ansferred from the serial receive shifter to the sci receive data register. t8 transmit data bit 8 this read/wr ite bit is the ninth data bit to be tr ansmitted when the sci system is con?gured f or nine data bit oper ation (m = 1). when the eight lo w order bits (bits 0C7) of a tr ansmit char acter are transf erred from the sci data register to the ser ial tr ansmit shift register , this bit (bit 8) is transferred to the ninth bit position of the shifter. m mode (select character format) the read/wr ite m-bit controls the char acter length f or both the tr ansmitter and receiv er at the same time . the 9th data bit is most commonly used as an e xtr a stop bit or in conjunction with the address mark wake-up method. it can also be used as a parity bit (see table 6-1). 1 (set) C start bit, 8 data bits, 1 stop bit. 0 (clear) C start bit, 9 data bits, 1 stop bit. wake wake-up mode select this bit allo ws the user to select the method f or receiver wake-up. the w ake bit can be read or written to any time. see table 6-1. 1 (set) C wake-up on address mark. 0 (clear) C wake-up on idle line. table 6-1 method of receiver wake-up wake m method of receiver wake-up 0 x detection of an idle line allows the next data type received to cause the receive data register to ?ll and produce an rdrf ?ag. 1 0 detection of a received one in the eighth data bit allows an rdrf ?ag and associated error ?ags. 1 1 detection of a received one in the ninth data bit allows an rdrf ?ag and associated error ?ags. x = dont care
motorola 6-12 mc68hc05b6 serial communications interface 6 cpol C clock polarity this bit allo ws the user to select the polar ity of the cloc ks to be sent to the sclk pin. it w orks in conjunction with the cpha bit to produce the desired cloc k-data relation (see figure 6-9 and figure 6-10). 1 (set) C steady high value at sclk pin outside transmission window. 0 (clear) C steady low value at sclk pin outside transmission window. this bit should not be manipulated while the transmitter is enabled. cpha C clock phase this bit allo ws the user to select the phase of the cloc ks to be sent to the sclk pin. this bit w orks in conjunction with the cpol bit to produce the desired cloc k-data relation (see figure 6-9 and figure 6-10). 1 (set) C sclk clock line activated at beginning of data bit. 0 (clear) C sclk clock line activated in middle of data bit. this bit should not be manipulated while the transmitter is enabled. figure 6-9 sci data clock timing diagram (m=0) idle or preceding transmission clock stop start lsb data m = 0 (8 data bits) idle or next lbcl bit controls last data clock transmission clock clock clock * * * * * start stop 0 1 2 3 4 5 6 msb 7 (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1)
mc68hc05b6 motorola 6-13 serial communications interface 6 lbcl C last bit clock this bit allo ws the user to select whether the cloc k associated with the last data bit tr ansmitted (msb) has to be output to the sclk pin. the cloc k of the last data bit is output to the sclk pin if the lbcl bit is a logic one, and is not output if it is a logic zero. the last bit is the 8th or 9th data bit tr ansmitted depending on the 8 or 9 bit f or mat selected b y m-bit (seetable 6-2). this bit should not be manipulated while the transmitter is enabled. figure 6-10 sci data clock timing diagram (m=1) table 6-2 sci clock on sclk pin data format m-bit lbcl bit number of clocks on sclk pin 8 bit 0 0 7 8 bit 0 1 8 9 bit 1 0 8 9 bit 1 1 9 idle or preceding transmission clock stop start lsb data m = 1 (9 data bits) idle or next lbcl bit controls last data clock transmission clock clock clock * * * * start stop 0 1 2 3 4 5 6 msb 7 * 8 (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1)
motorola 6-14 mc68hc05b6 serial communications interface 6 6.11.3 serial communications control register 2 (sccr2) the sci control register 2 (sccr2) pro vides the control bits that enab le/disab le individual sci functions. tie transmit interrupt enable 1 (set) C tdre interrupts enabled. 0 (clear) C tdre interrupts disabled. tcie transmit complete interrupt enable 1 (set) C tc interrupts enabled. 0 (clear) C tc interrupts disabled. rie receiver interrupt enable 1 (set) C rdrf and or interrupts enabled. 0 (clear) C rdrf and or interrupts disabled. ilie idle line interrupt enable 1 (set) C idle interrupts enabled. 0 (clear) C idle interrupts disabled. te transmitter enable when the tr ansmit enab le bit is set, the tr ansmit shift register output is applied to the tdo line and the corresponding cloc ks are applied to the sclk pin. depending on the state of control bit m (sccr1), a preamble of 10 (m = 0) or 11 (m = 1) consecutive ones is transmitted when software sets the te bit from a cleared state. if a tr ansmission is in prog ress and a z ero is wr itten to te, the tr ansmitter will w ait until after the present b yte has been tr ansmitted bef ore placing the tdo and the sclk pin in the idle , high impedance state. if the te bit has been wr itten to a z ero and then set to a one bef ore the current b yte is tr ansmitted, the transmitter will wait for that byte to be tr ansmitted and will then initiate tr ansmission of a new preamble . after this latest tr ansmission, and pro vided the tdre bit is set (no ne w data to tr ansmit), the line remains idle (dr iv en high while te = 1); otherwise , normal transmission occurs. this function allows the user to neatly terminate a transmission sequence. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci control (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000
mc68hc05b6 motorola 6-15 serial communications interface 6 after loading the last b yte in the ser ial comm unications data register and receiving the tdre ?ag, the user should clear te. transmission of the last b yte will then be completed and the line will go idle. 1 (set) C transmitter enabled. 0 (clear) C transmitter disabled. re receiver enable 1 (set) C receiver enabled. 0 (clear) C receiver disabled. when re is clear (receiv er disab led) all the status bits associated with the receiv er (rdrf, idle, or, nf and fe) are inhibited. rwu receiver wake-up when the receiv er wak e-up bit is set b y the user softw are , it puts the receiv er to sleep and enab les the wak e-up function. the type of w ake-up mode for the receiver is determined by the wake bit discussed abov e (in the sccr1). when the r wu bit is set, no status ?ags will be set. flags which were set previously will not be cleared when rwu is set. if the w ake bit is cleared, r wu is cleared b y the sci logic after receiving 10 (m = 0) or 11 (m =1) consecutive ones . under these conditions , r wu cannot be set if the line is idle . if the w ake bit is set, r wu is cleared after receiving an address bit. the rdrf ?ag will then be set and the address byte stored in the receiver data register. sbk send break if the send break bit is toggled set and cleared, the tr ansmitter sends 10 (m = 0) or 11 (m = 1) z eros and then re ver ts to idle sending data. if sbk remains set, the tr ansmitter will contin ually send whole b loc ks of z eros (sets of 10 or 11) until cleared. at the completion of the break code , the transmitter sends at least one high bit to guarantee recognition of a valid start bit.
motorola 6-16 mc68hc05b6 serial communications interface 6 6.11.4 serial communications status register (scsr) the serial comm unications status register (scsr) pro vides inputs to the interr upt logic circuits f or gener ation of the sci system interr upt. in addition, a noise ?ag bit and a fr aming error bit are also contained in the scsr. tdre transmit data register empty ?ag this bit is set when the contents of the tr ansmit data register are tr ansf erred to the ser ial shift register. ne w data will not be tr ansmitted unless the scsr register is read bef ore wr iting to the transmit data register to clear the tdre ?ag. if the tdre bit is clear , this indicates that the tr ansf er has not y et occurred and a wr ite to the ser ial comm unications data register will o verwr ite the pre vious v alue . the tdre bit is cleared b y accessing the ser ial comm unications status register (with tdre set) f ollow ed b y wr iting to the serial communications data register. tc transmit complete ?ag this bit is set to indicate that the sci tr ansmitter has no meaningful inf or mation to tr ansmit (no data in shifter , no preamb le , no break). when tc is set the ser ial line will go idle (contin uous mark). the tc bit is cleared b y accessing the serial communications data register (with tc set) follow ed b y wr iting to the ser ial comm unications data register . it does not inhibit the tr ansmitter function in any way. rdrf receive data register full ?ag this bit is set when the contents of the receiver serial shift register are transferred to the receiver data register. if m ultiple errors are detected in an y one received w ord, the nf and rdrf bits will be aff ected as appropr iate dur ing the same cloc k cycle . the rdrf bit is cleared when the ser ial comm unications status register is accessed (with rdrf set) f ollowed by a read of the serial communications data register. idle idle line detected ?ag this bit is set when a receiv er idle line is detected (the receipt of a minim um of ten/ele ven consecutiv e 1s). this bit will not be set b y the idle line condition when the r wu bit is set. this allo ws a receiv er that is not in the w ak e-up mode to detect the end of a message , detect the preamb le of a ne w message or resynchroniz e with the tr ansmitter . the idle bit is cleared b y accessing the ser ial comm unications status register (with idle set) f ollow ed b y a read of the ser ial comm unications data register . once cleared, idle will not be set again until after rdrf has been set, (i.e. until after the line has been active and becomes idle again). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u
mc68hc05b6 motorola 6-17 serial communications interface 6 or overrun error ?ag this bit is set when a ne w b yte is ready to be tr ansf erred from the receiv er shift register to the receiver data register and the receiv e data register is already full (rdrf bit is set). data tr ansfer is inhibited until the rdrf bit is cleared. data in the ser ial comm unications data register is v alid in this case, b ut additional data receiv ed during an overr un condition (including the b yte causing the overrun) will be lost. the or bit is cleared when the ser ial comm unications status register is accessed (with or set) followed by a read of the serial communications data register. nf noise error ?ag this bit is set if there is noise on a v alid start bit, an y of the data bits or on the stop bit. the nf bit is not set b y noise on the idle line nor b y invalid start bits. if there is noise, the nf bit is not set until the rdrf ?ag is set. each data bit is sampled three times as described in section 6.7. the nf bit represents the status of the b yte in the ser ial comm unications data register . f or the byte being received (shifted in) there will be also a working noise ?ag, the value of which will be transf erred to the nf bit when the ser ial data is loaded into the ser ial comm unications data register . the nf bit does not gener ate an interr upt because the rdrf bit gets set with nf and can be used to generate the interrupt. the nf bit is cleared when the ser ial comm unications status register is accessed (with nf set) followed by a read of the serial communications data register. fe framing error ?ag this bit is set when the w ord boundar ies in the bit stream are not synchroniz ed with the receiver bit counter (generated b y the reception of a logic z ero bit where a stop bit w as expected). the fe bit re?ects the status of the b yte in the receiv e data register and the tr ansf er from the receiv e shifter to the receiv e data register is inhibited b y an o verr un. the fe bit is set dur ing the same cycle as the rdrf bit but does not get set in the case of an overrun (or). the framing error ?ag inhibits further transfer of data into the receive data register until it is cleared. the fe bit is cleared when the ser ial comm unications status register is accessed (with fe set) followed by a read of the serial communications data register.
motorola 6-18 mc68hc05b6 serial communications interface 6 6.11.5 baud rate register (baud) the baud rate register provides the means to select two different or equivalent baud rates for the transmitter and receiver. scp1, scp0 serial prescaler select bits these read/wr ite bits deter mine the prescale f actor, np, b y which the inter nal processor cloc k is divided bef ore it is applied to the tr ansmitter and receiv er r ate control dividers , nt and nr. this common prescaled output is used as the input to a divider that is controlled b y the scr0Cscr2 bits for the sci receiver, and by the sct0Csct2 bits for the transmitter. sct2, sct1,sct0 sci rate select bits (transmitter) these three read/wr ite bits select the baud r ates f or the tr ansmitter . the prescaler output is divided by the factors shown in table 6-4. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci baud rate (baud) $000d scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 00uu uuuu table 6-3 first prescaler stage scp1 scp0 prescaler division ratio (np) 0 0 1 0 1 3 1 0 4 1 1 13 table 6-4 second prescaler stage (transmitter) sct2 sct1 sct0 transmitter division ratio (nt) 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
mc68hc05b6 motorola 6-19 serial communications interface 6 scr2, scr1, scr0 sci rate select bits (receiver) these three read/write bits select the baud rates for the receiver. the prescaler output described above is divided by the factors shown in table 6-5. the following equations are used to calculate the receiver and transmitter baud rates: where: np = prescaler divide ratio nt = transmitter baud rate divide ratio nr = receiver baud rate divide ratio baudtx = transmitter baud rate baudrx = receiver baud rate f osc = oscillator frequency 6.12 baud rate selection the ?e xibility of the baud r ate gener ator allo ws man y diff erent baud r ates to be selected. a particular baud rate may be generated in several ways by manipulating the various prescaler and division r atio bits . t ab le 6-6 sho ws the baud r ates that can be achie v ed, f or ?v e typical cr ystal frequencies . these are eff ectiv ely the highest baud r ates which can be achie v ed using a giv en crystal. table 6-5 second prescaler stage (receiver) scr2 scr1 scr0 receiver division ratio (nr) 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 baudtx f osc 32 np n t ---------------------------------- = baudrx f osc 32 np nr -------------------------------- -- - =
motorola 6-20 mc68hc05b6 serial communications interface 6 note: the examples shown abov e do not apply when the par t is oper ating in slo w mode (see section 2.4.3). table 6-6 sci baud rate selection crystal frequency C f osc (mhz) scp1 scp0 sct/r2 sct/r1 sct/r0 np nt/nr 4.194304 4.00 2.4576 2.00 1.8432 0 0 0 0 0 1 1 131072 125000 76800 62500 57600 0 0 0 0 1 1 2 65536 62500 38400 31250 28800 0 0 0 1 0 1 4 32768 31250 19200 15625 14400 0 0 0 1 1 1 8 16384 15625 9600 7813 7200 0 0 1 0 0 1 16 8192 7813 4800 3906 3600 0 0 1 0 1 1 32 4096 3906 2400 1953 1800 0 0 1 1 0 1 64 2048 1953 1200 977 900 0 0 1 1 1 1 128 1024 977 600 488 450 0 1 0 0 0 3 1 43691 41667 25600 20833 19200 0 1 0 0 1 3 2 21845 20833 12800 10417 9600 0 1 0 1 0 3 4 10923 10417 6400 5208 4800 0 1 0 1 1 3 8 5461 5208 3200 2604 2400 0 1 1 0 0 3 16 2731 2604 1600 1302 1200 0 1 1 0 1 3 32 1365 1302 800 651 600 0 1 1 1 0 3 64 683 651 400 326 300 0 1 1 1 1 3 128 341 326 200 163 150 1 0 0 0 0 4 1 32768 31250 19200 15625 14400 1 0 0 0 1 4 2 16384 15625 9600 7813 7200 1 0 0 1 0 4 4 8192 7813 4800 3906 3600 1 0 0 1 1 4 8 4096 3906 2400 1953 1800 1 0 1 0 0 4 16 2048 1953 1200 977 900 1 0 1 0 1 4 32 1024 977 600 488 450 1 0 1 1 0 4 64 512 488 300 244 225 1 0 1 1 1 4 128 256 244 150 122 113 1 1 0 0 0 13 1 10082 9615 5908 4808 4431 1 1 0 0 1 13 2 5041 4808 2954 2404 2215 1 1 0 1 0 13 4 2521 2404 1477 1202 1108 1 1 0 1 1 13 8 1260 1202 738 601 554 1 1 1 0 0 13 16 630 601 369 300 277 1 1 1 0 1 13 32 315 300 185 150 138 1 1 1 1 0 13 64 158 150 92 75 69 1 1 1 1 1 13 128 79 75 46 38 35
mc68hc05b6 motorola 6-21 serial communications interface 6 6.13 sci during stop mode when the mcu enters st op mode , the baud r ate generator driving the receiver and transmitter is shut do wn. this stops all sci activity . both the receiv er and the tr ansmitter are unab le to operate. if the st op instr uction is e x ecuted dur ing a tr ansmitter tr ansfer , that tr ansf er is halted. when stop mode is exited as a result of an external interrupt, that particular transmission resumes. if the receiv er is receiving data when the st op instruction is executed, received data sampling is stopped (baud generator stops) and the rest of the data is lost. warning: for the above reasons, all sci tr ansactions should be in the idle state when the st op instruction is executed. 6.14 sci during wait mode the sci system is not aff ected b y w ait mode and contin ues nor mal oper ation. an y v alid sci interr upt will w ak e-up the system. if required, the sci system can be disab led pr ior to enter ing w ait mode b y wr iting a z ero to the tr ansmitter and receiv er enab le bits in the ser ial comm unication control register 2 at $000f . this action will result in a reduction of po wer consumption during wait mode.
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mc68hc05b6 motorola 7-1 pulse length d/a converters 7 7 pulse length d/a converters the pulse length d/a converter (plm) system wor ks in conjunction with the timer to e xecute two 8-bit d/a conversions, with a choice of two repetition rates. (see figure 7-1.) figure 7-1 plm system block diagram plma register plmb a register buffer b register a comparator b latch zero detector sfa bit sfb d/a pin timer bus from timer data bus 8 16 multiplexer a b buffer register comparator multiplexer plma plmb d/a r s bit zero detector 8 16 8 8 pin latch r s
motorola 7-2 mc68hc05b6 pulse length d/a converters 7 the d/a converter has two data registers associated with it, plma and plmb. this is a dual 8-bit resolution d/a con ver ter associated with tw o output pins (plma and plmb). the outputs are pulse length modulated signals whose duty cycle r atio ma y be modi?ed. these signals can be used directly as plms , or the ?ltered a ver age ma y be used as gener al pur pose analog outputs. the longest repetition per iod is 4096 times the prog rammab le timer cloc k per iod (cpu cloc k multiplied by f our), and the shor test repetition per iod is 256 times the prog rammab le timer cloc k period (the repetition rate frequencies for a 4 mhz crystal are 122 hz and 1953 hz respectively). registers plma ($0a) and plmb ($0b) are associated with the pulse length v alues of the tw o counters . a v alue of $00 loaded into these registers results in a contin uously lo w output on the corresponding d/a output pin. a v alue of $80 results in a 50% duty cycle output, and so on, to the maximum v alue $ff corresponding to an output which is at 1 f or 255/256 of the cycle . when the mcu mak es a wr ite to register plma or plmb the ne w v alue will only be pic k ed up b y the d/a conver ters at the end of a complete cycle of con v ersion. this results in a monotonic change of the dc component at the output without o v ershoots or vicious star ts (a vicious star t is an output which giv es totally erroneous plm dur ing the per iod immediately f ollo wing an update of the plm d/a registers). this f eature is achie v ed b y doub le b uffer ing of the plm d/a registers . examples of pwm output waveforms are shown in figure 7-2. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 figure 7-2 plm output waveform examples 256 t 255 t 128 t t $80 $ff t = 4 cpu clocks in fast mode and 64 cpu clocks in slow mode 128 t t $00 $01 255 t
mc68hc05b6 motorola 7-3 pulse length d/a converters 7 note: since the plm system uses the timer counter , plm results will be aff ected while resetting the timer counter . both d/a registers are reset to $00 dur ing po w er-on or e xter nal reset. w ait mode does not aff ect the output w avefor m of the d/a con ver ters . 7.1 miscellaneous register sfa slow or fast mode selection for plma this bit allo ws the user to select the slo w or f ast mode of the plma pulse length modulation output. 1 (set) C slow mode plma (4096 x timer clock period). 0 (clear) C fast mode plma (256 x timer clock period). sfb slow or fast mode selection for plmb this bit allo ws the user to select the slo w or f ast mode of the plmb pulse length modulation output. 1 (set) C slow mode plmb (4096 x timer clock period). 0 (clear) C fast mode plmb (256 x timer clock period). the highest speed of the plm system corresponds to the frequency of the t of bit being set, multiplied by 256. the low est speed of the plm system corresponds to the frequency of the t of bit being set, m ultiplied b y 16. because the sf a bit and sfb bit are not doub le b uff ered, it is mandator y to set them to the desired v alues bef ore wr iting to the plm registers; not doing so could temporarily give incorrect values at the plm outputs. sm slow mode 1 (set) C the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sections of the device, including sci, a/d and timer. 0 (clear) C the system runs at normal bus speed (f osc /2). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000?
motorola 7-4 mc68hc05b6 pulse length d/a converters 7 the sm bit is cleared by external or power-on reset. the sm bit is automatically cleared when entering stop mode. note: the bits that are shown shaded in the above representation are explained individually in the rele v ant sections of this man ual. the complete register plus an e xplanation of each bit can be found in section 3.8 7.2 plm clock selection the slow/f ast mode of the plm d/a con ver ters is selected b y bits 1, 2, and 3 of the miscellaneous register at address $000c (sfa bit for plma and sfb bit for plmb). the slow/fast mode has no effect on the d/a converters 8-bit resolution (see figure 7-3). 7.3 plm during stop mode on entering stop mode , the plm outputs remain at their par ticular lev el. when st op mode is e xited b y an interr upt, the plm systems resume regular oper ation. if st op mode is e xited b y power-on or external reset the registers values are forced to $00. 7.4 plm during wait mode the plm system is not affected by wait mode and continues normal operation. figure 7-3 plm clock selection f osc ?2 ?32 sm bit = 0 sm bit = 1 ?4 x4096 x256 sf bit = 1 sf bit = 0 timer clock plm clock bus frequency (f op )
mc68hc05b6 motorola 8-1 analog to digital converter 8 8 analog to digital converter the analog to digital con ver ter system consists of a single 8-bit successiv e appro ximation conver ter and a sixteen channel m ultiplexer . eight of the channels are connected to the pd0/an0 C pd7/an7 pins of the mc68hc05b6 and the other eight channels are dedicated to internal reference points for test functions . the channel input pins do not ha ve any internal output driver circuitr y connected to them because such circuitr y w ould load the analog input signals due to output b uff er leakage current. there is one 8-bit result data register (address $08) and one 8-bit status/control register (address $09). the a/d con ver ter is r atiometr ic and tw o dedicated pins , vrh and vrl, are used to supply the ref erence v oltage le v els f or all analog inputs . these pins are used in pref erence to the system pow er supply lines because an y v oltage drops in the bonding wires of the hea vily loaded supply pins could degrade the accuracy of the a/d conversion. an input voltage equal to or greater than v rh con ver ts to $ff (full scale) with no o ver?o w indication and an input v oltage equal to v rl converts to $00. the a/d con ver ter can oper ate from either the b us cloc k or an inter nal rc type oscillator . the inter nal rc type oscillator is activ ated b y the adrc bit in the a/d status/control register (adst at) and can be used to giv e a suf?ciently high cloc k r ate to the a/d con ver ter when the b us speed is too lo w to pro vide accur ate results . when the a/d con ver ter is not being used it can be disconnected, by clear ing the adon bit in the adst a t register , in order to sa ve pow er (see section 8.2.3). f or fur ther inf or mation on a/d con ver ter oper ation please ref er to the m68hc11 ref erence manual m68hc11rm/ad. 8.1 a/d converter operation the a/d conver ter consists of an analog m ultiplexer , an 8-bit digital to analog con verter capacitor array, a comparator and a successive approximation register (sar) (see figure 8-1). there are elev en options that can be selected b y the multiplexer; an0Can7, vrh, (vrh+vrl)/2 or vrl. selection is done via the chx bits in the adstat register (see section 8.2.3). an0Can7 are the only input points f or a/d con version oper ations; the others are ref erence points that can be used for test purposes.
motorola 8-2 mc68hc05b6 analog to digital converter 8 the a/d ref erence input (an0Can7) is applied to a precision inter nal d/a converter. control logic driv es this d/a con ver ter and the analog output is successiv ely compared with the analog input sampled at the beginning of the conversion. the conversion is monotonic with no missing codes. the result of each successiv e compar ison is stored in the sar and, when the con v ersion is complete, the contents of the sar are transferred to the read-only result data register ($08), and the conversion complete ?ag, coco, is set in the a/d status/control register ($09). warning: any wr ite to the a/d status/control register will abor t the current con version, reset the conversion complete ?ag and start a new conversion on the selected channel. at po w er-on or e xter nal reset, both the adrc and adon bits are cleared; thus the a/d is disab led. figure 8-1 a/d converter block diagram an0 vrh (vrh+vrl)/2 vrl analog mux a/d result register (addata) $08 8-bit capacitive dac with sample and hold vrh vrl result a/d status/control register (adstat)$09 (channel assignment) coco adrc adon 0 ch3 ch2 ch1 ch0 an1 an2 an3 an4 an5 an6 an7 successive approximation register (sar) and control
mc68hc05b6 motorola 8-3 analog to digital converter 8 8.2 a/d registers 8.2.1 port d data register (portd) por t d is an input-only por t which routes the eight analog inputs to the a/d con verter . when the a/d converter is disabled, the pins are con?gured as standard input-only port pins, which can be read via the port d data register. note: when the a/d function is enab led, pins pd0Cpd7 will act as analog inputs . using a pin or pins as a/d inputs does not aff ect the ability to read por t d as static inputs; ho wever, reading por t d dur ing an a/d con v ersion sequence ma y inject noise on the analog inputs and result in reduced accuracy of the a/d result. perfor ming a digital read of por t d with le v els other than v dd or v ss on the pins will result in g reater pow er dissipation dur ing the read cycle , and ma y give unpredictable results on the corresponding port d pins. 8.2.2 a/d result data register ( addata ) addat a is a read-only register which is used to store the results of a/d con versions. each result is loaded into the register from the sar and the con v ersion complete ?ag, coco , in the adst at register is set. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d data (addata) $0008 0000 0000
motorola 8-4 mc68hc05b6 analog to digital converter 8 8.2.3 a/d status/control register (adstat) coco conversion complete ?ag 1 (set) C coco is set each time a conversion is complete, allowing the new result to be read from the a/d result data register ($08). the converter then starts a new conversion. 0 (clear) C coco is cleared b y reading the result data register or wr iting to the status/control register. reset clears the coco ?ag. adrc a/d rc oscillator control the adrc bit allo ws the user to control the a/d rc oscillator , which is used to pro vide a suf?ciently high clock rate to the a/d to ensure accuracy when the chip is running at low speeds. 1 (set) C when the adrc bit is set, the a/d rc oscillator is tur ned on and, if adon is set, the a/d r uns from the rc oscillator cloc k. see tab le 8-1. 0 (clear) C when the adrc bit is cleared, the a/d rc oscillator is turned-off and, if adon is set, the a/d runs from the cpu clock. when the a/d rc oscillator is tur ned on, it tak es a time t adrc to stabiliz e (see t ab le 11-7 and table 11-8). during this time a/d conversion results may be inaccurate. note: if the mcu bus clock falls below 1mhz, the a/d rc oscillator should be switched on. power-on or external reset clears the adrc bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 table 8-1 a/d clock selection adrc adon rc oscillator a/d converter comments 0 0 off off a/d switched off. 0 1 off on a/d using cpu clock. 1 0 on off allows the rc oscillator to stabilize. 1 1 on on a/d using rc oscillator clock.
mc68hc05b6 motorola 8-5 analog to digital converter 8 adon a/d converter on the adon bit allows the user to enable/disable the a/d converter. 1 (set) C a/d converter is switched on. 0 (clear) C a/d converter is switched off. when the a/d con ver ter is s witched on, it tak es a time t adon f or the current sources to stabiliz e (see table 11-7 and table 11-8). during this time a/d conversion results may be inaccurate. power-on or external reset will clear the adon bit, thus disabling the a/d converter. ch3Cch0 a/d channels 3, 2, 1 and 0 the ch3Cch0 bits allow the user to determine which channel of the a/d converter multiplexer is selected. see table 8-2 for channel selection. reset clears the ch0Cch3 bits. 8.3 a/d converter during stop mode when the mcu enters st op mode with the a/d con verter tur ned on, the a/d cloc ks are stopped and the a/d con ver ter is disab led f or the dur ation of st op mode , including the 4064 cycles start-up time. if the a/d rc oscillator is in operation it will also be disabled. table 8-2 a/d channel assignment ch3 ch2 ch1 ch0 channel selected 0 0 0 0 an0 0 0 0 1 an1 0 0 1 0 an2 0 0 1 1 an3 0 1 0 0 an4 0 1 0 1 an5 0 1 1 0 an6 0 1 1 1 an7 1 0 0 0 vrh pin (high) 1 0 0 1 (vrh + vrl) / 2 1 0 1 0 vrl pin (low) 1 0 1 1 vrl pin (low) 1 1 0 0 vrl pin (low) 1 1 0 1 vrl pin (low) 1 1 1 0 vrl pin (low) 1 1 1 1 vrl pin (low)
motorola 8-6 mc68hc05b6 analog to digital converter 8 8.4 a/d converter during wait mode the a/d converter is not affected by wait mode and continues normal operation. in order to reduce po w er consumption the a/d con ver ter can be disconnected, under softw are control using the adon bit and the adrc bit in the a/d status/control register at $0009, bef ore entering wait mode. 8.5 port d analog input the exter nal analog v oltage v alue to be processed b y the a/d con ver ter is sampled on an inter nal capacitor through a resistive path, provided by input-selection s witches and a sampling aper ture time s witch, as sho wn in figure 8-2. sampling time is limited to 12 b us cloc k cycles . after sampling, the analog v alue is stored on the capacitor and held until the end of con version. during this hold time , the analog input is disconnected from the inter nal a/d system and the e xternal voltage source sees a high impedance input. the equiv alent analog input dur ing sampling is an rc lo w-pass ?lter with a minim um resistance of 50 k? and a capacitance of at least 10pf . it should be noted that these are typical v alues measured at room temperature. figure 8-2 electrical model of an a/d input pin analog input pin input protection device v rl < 2pf + ~20v - ~0.7v 400 na junction leakage 50k? 10pf dac capacitance note: the analog switch is closed during the 12 cycle sample time only.
mc68hc05b6 motorola 9-1 resets and interrupts 9 9 resets and interrupts 9.1 resets the mc68hc05b6 can be reset in three w ays: by the initial power-on reset function, by an active lo w input to the reset pin or b y a computer oper ating proper ly (cop) w atchdog reset. an y of these resets will cause the prog r am to go to its star ting address , speci?ed b y the contents of memor y locations $1ffe and $1fff , and cause the interr upt mask bit in the condition code register to be set. figure 9-1 reset timing diagram v dd reset 1fff 1ffe 1ffe 1ffe new 1fff 1ffe 1ffe 1ffe pc osc1 new pc internal internal processor clock 1ffe op code new pcl new pch t vddr op code new pcl new pch address bus internal data bus t oxov t cyc t porl 1ffe program execution begins program execution begins t rl (or t dogl ) (internal power-on reset) (external hardware reset) v dd threshold (1-2v typical) reset sequence reset sequence
motorola 9-2 mc68hc05b6 resets and interrupts 9 9.1.1 power-on reset a po w er-on reset occurs when a positiv e tr ansition is detected on vdd . the po w er-on reset function is str ictly f or po w er tur n-on conditions and should not be used to detect drops in the po wer supply v oltage . the po w er-on circuitr y pro vides a stabilization dela y (t porl ) from when the oscillator becomes activ e . if the e xternal reset pin is lo w at the end of this dela y then the processor remains in the reset state until reset goes high. the user m ust ensure that the v oltage on vdd has risen to a point where the mcu can operate properly by the time t porl has elapsed. if there is doubt, the e xternal reset pin should remain lo w until the v oltage on vdd has reached the speci?ed minim um oper ating v oltage . this ma y be accomplished b y connecting an e xternal rc circuit to this pin to generate a power-on reset (por). in this case, the time constant must be great enough to allow the oscillator circuit to stabilize. dur ing po w er-on reset, the reset pin is dr iv en lo w dur ing a t porl dela y star t-up sequence . t porl is de?ned b y a user speci?ed mask option to be either 16 cycles or 4064 cycles (see section 1.2). a softw are distinction betw een a po w er-on reset and an e xter nal reset can be made using the por bit in the miscellaneous register (see section 9.1.2). 9.1.2 miscellaneous register por power-on reset bit this bit is set each time the de vice is powered on. therefore , the state of the por bit allo ws the user to make a software distinction between a power-on and an exter nal reset. this bit cannot be set by software and is cleared by writing it to zero. 1 (set) C a power-on reset has occurred. 0 (clear) C no power-on reset has occurred. note: the bits sho wn shaded in the abo v e representation are e xplained individually in the relevant sections of this man ual. the complete register plus an e xplanation of each bit can be found in section 3.8. (1) the por bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000?
mc68hc05b6 motorola 9-3 resets and interrupts 9 9.1.3 reset pin when the oscillator is r unning in a stab le condition, the mcu is reset when a logic z ero is applied to the reset input f or a minim um per iod of 1.5 machine cycles (t cyc ). an inter nal schmitt t rigger is used to impro v e noise imm unity on this pin. when the reset pin goes high, the mcu will resume operation on the following cycle . when a reset condition occurs inter nally, i.e. from por or the cop watchdog, the reset pin provides an active-low open dr ain output signal which ma y be used to reset external hardware. current limitation to protect the pull-down device is provided in case an rc type external reset circuit is used. 9.1.4 computer operating properly (cop) watchdog reset the w atchdog counter system consists of a divide-b y-8 counter, preceded by a ?xed divide-by-4 and a ?x ed divide-b y-256 prescaler , plus control logic as sho wn in figure 9-2. the divide-b y-8 counter can be reset by software. warning: the input to the w atchdog system is der iv ed from the carr y output of bit 7 of the free r unning timer counter . theref ore , a reset of the timer ma y aff ect the per iod of the watchdog timeout. the watchdog system can be automatically enabled, following power-on or external reset, via a mask option (see section 1.2), or it can be enabled by software by writing a 1 to the wdog bit in the miscellaneous register at $000c (see section 9.1.2). once enab led, the watchdog system figure 9-2 watchdog system block diagram ? 256 (bit 7 of free f osc /2 f osc /32 main cpu ? 8 w atchdog counter wdog bit control logic latch + reset schmitt input protection trigger pin power-on s r enable reset clock ? 4 prescaler running counter)
motorola 9-4 mc68hc05b6 resets and interrupts 9 cannot be disabled by software (writing a zero to the wdog bit has no effect at any time). in addition, the wdog bit acts as a reset mechanism f or the watchdog counter. writing a 1 to this bit clears the counter to its initial value and prevents a watchdog timeout. wdog watchdog enable/disable the wdog bit can be used to enab le the watchdog timer previously disabled b y a mask option. following a w atchdog reset the state of the wdog bit is as de?ned b y the mask option speci?ed. 1 (set) C watchdog enabled and counter cleared. 0 (clear) C the watchdog cannot be disabled by software; writing a zero to this bit has no effect. the divide-by-8 watchdog counter will gener ate a main reset of the chip when it reaches its ?nal state; se v en cloc ks are necessar y to br ing the w atchdog counter from its clear state to its ?nal state. this reset appears after time t dog since the last clear or since the enable of the watchdog counter system. the w atchdog counter, therefore , has to be cleared per iodically, by software, with a period less than t dog . the reset generated by the w atchdog system is apparent at the reset pin (see figure 9-2). the reset pin lev el is re-entered in the control logic , and when it has been maintained at le vel zero for a minimum of t dogl , the reset pin is released. 9.1.4.1 cop watchdog during stop mode the stop instruction is inhibited when the watchdog system is enabled. if a stop instruction is ex ecuted while the w atchdog system is enab led, then a w atchdog reset will occur as if there w ere a watchdog timeout. in the case of a watchdog reset due to a stop instruction, the oscillator will not be aff ected, thus there will be no t porl cycles star t-up delay . on star t-up , the w atchdog will be con?gured according to the user speci?ed mask option. 9.1.4.2 cop watchdog during wait mode the state of the w atchdog during w ait mode is selected via a mask option (see section 1.2) to be one of the options below: w atchdog enab led the w atchdog counter will contin ue to oper ate dur ing w ait mode and a reset will occur after time t dog . w atchdog disab led on enter ing w ait mode , the w atchdog counter system is reset and disabled. on exiting wait mode the counter resumes normal operation.
mc68hc05b6 motorola 9-5 resets and interrupts 9 9.1.5 functions affected by reset when processing stops within the mcu f or an y reason, i.e . pow er-on reset, e xter nal reset or the ex ecution of a st op or w ait instr uction, v ar ious inter nal functions of the mcu are aff ected. tab le 9-1 sho ws the resulting action of an y type of system reset, b ut not necessar ily in the order in which the y occur . table 9-1 effect of reset, por, stop and wait function/effect reset por wait stop timer prescaler set to zero x x C C timer counter set to $fffc x x C C all timer enable bits cleared (disable) x x C C data direction registers cleared (inputs) x x C C stack pointer set to $00ff x x C C force internal address bus to restart x x C C vector $1ffe, $1fff x x C C interrupt mask bit (i-bit ccr) set to 1 x x C C interrupt mask bit (i-bit ccr) cleared C C x x set interrupt enable bit (inte) x x C C set por bit in miscellaneous register C x C C reset stop latch x x C C reset irq latch x x C C reset wait latch x x C C sci disabled x x C C sci status bits cleared (except tdre and tc) x x C C sci interrupt enable bits cleared x x C C sci status bits tdre and tc set x x C C oscillator disabled for 4064 cycles C x C x timer clock cleared C x C x sci clock cleared C x C x a/d disabled x x C x sm bit in the miscellaneous register cleared x x C x watchdog counter reset x x x x wdog bit in the miscellaneous register reset x x C x eeprom control bits (see section 3.5.1) x x C x x = described action takes place C = descr ibed action does not tak e place
motorola 9-6 mc68hc05b6 resets and interrupts 9 9.2 interrupts the mcu can be interr upted b y f our diff erent sources: three maskab le hardw are interr upts and one non maskable software interrupt: ? external signal on the irq pin ? serial communications interface (sci) ? programmable timer ? software interrupt instruction (swi) interr upts cause the processor to sa v e the register contents on the stac k and to set the interr upt mask (i-bit) to pre v ent additional interr upts . the r ti instr uction (ret ur n from interr upt) causes the register contents to be reco v ered from the stac k and nor mal processing to resume . while ex ecuting the r ti instr uction, the v alue of the i-bit is replaced b y the corresponding i-bit stored on the stack. unlike reset, hardware interr upts do not cause the current instr uction ex ecution to be halted, b ut are considered pending until the current instr uction is complete . the current instr uction is the one already f etched and being oper ated on. when the current instr uction is complete , the processor chec ks all pending hardw are interr upts . if interr upts are not mask ed (i-bit clear) and the corresponding interr upt enab le bit is set, the processor proceeds with interr upt processing; otherwise, the next instruction is fetched and executed. note: pow er-on and e xter nal reset clear all interr upt enable bits, b ut set the inte bit in the miscellaneous register, thus preventing interrupts during the reset sequence. 9.2.1 interrupt priorities each potential interr upt source is assigned a pr ior ity le v el, which means that if more than one interr upt is pending at the same time , the processor will ser vice the one with the highest pr iority ?rst. f or e xample , if both an e xter nal interr upt and a timer interr upt are pending after an instr uction execution, the external interrupt is serviced ?rst. tab le 9-2 sho ws the relativ e pr ior ity of all the possib le interr upt sources . figure 9-3 sho ws the interrupt processing ?ow. 9.2.2 nonmaskable software interrupt (swi) the softw are interr upt (swi) is an e xecutab le instr uction and a nonmaskab le interr upt: it is ex ecuted regardless of the state of the i-bit in the ccr. if the i-bit is z ero (interrupts enabled), swi is e x ecuted after interr upts that w ere pending when the swi w as f etched, b ut bef ore interr upts
mc68hc05b6 motorola 9-7 resets and interrupts 9 gener ated after the swi w as f etched. the swi interr upt ser vice routine address is speci?ed b y the contents of memory locations $1ffc and $1ffd. 9.2.3 maskable hardware interrupts if the interr upt mask bit in the ccr is set, all maskab le interr upts (inter nal and e xter nal) are masked. clearing the i-bit allows interrupt processing to occur. note: the inter nal interr upt latch is cleared in the ?rst par t of the interr upt ser vice routine; therefore , one e xter nal interr upt pulse could be latched and ser viced as soon as the i-bit is cleared. 9.2.3.1 external interrupt ( irq) if the interr upt mask in the condition code register has been cleared and the interr upt enable bit (inte) is set and the signal on the e xternal interrupt pin ( irq) satis?es the condition selected by the option control bits (intp and intn), then the e xternal interr upt is recogniz ed. inte, intp and intn are all bits contained in the miscellaneous register at $000c . when the interr upt is recogniz ed, the current state of the cpu is pushed onto the stac k and the i-bit is set. this masks further interrupts until the present one is serviced. the external interrupt service routine address is speci?ed by the content of memory locations $1ffa and $1ffb. table 9-2 interrupt priorities source register flags vector address priority reset $1ffe, $1fff highest software interrupt (swi) $1ffc, $1ffd external interrupt ( irq) $1ffa, $1ffb timer input captures tsr icf1, icf2 $1ff8, $1ff9 timer output compares tsr ocf1, ocf2 $1ff6, $1ff7 timer over?ow tsr tof $1ff4, $1ff5 serial communications interface (sci) scsr tdre, tc, or, rdrf, idle $1ff2, $1ff3 lowest
motorola 9-8 mc68hc05b6 resets and interrupts 9 figure 9-3 interrupt ?ow chart reset is i-bit set? irq external interrupt? timer internal interrupt? sci internal interrupt? fetch next instruction ex ecute instr uction clear irq request latch stack pc, x, a, cc set i-bit load pc from: irq: $1ffa-$1ffb timer ic: $1ff8-$1ff9 timer oc: $1ff6-$1ff7 timer ovf:$1ff4-$1ff5 sci: $1ff2-$1ff3 complete interr upt routine and e x ecute r ti
mc68hc05b6 motorola 9-9 resets and interrupts 9 9.2.3.2 miscellaneous register note: the bits sho wn shaded in the abo v e representation are e xplained individually in the relevant sections of this man ual. the complete register plus an e xplanation of each bit can be found in section 3.8. intp, intn external interrupt sensitivity options these tw o bits allo w the user to select which edge the irq pin is sensitiv e to as sho wn in t able 9-3. both bits can be wr itten to only while the i-bit is set, and are cleared b y power-on or external reset. therefore the device is initialised with negative edge and low level sensitivity. inte external interrupt enable 1 (set) C external interrupt function ( irq) enabled. 0 (clear) C external interrupt function ( irq) disabled. the inte bit can be written to only while the i-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. tab le 9-3 descr ibes the v arious trigger ing options a vailable for the irq pin, ho wev er it is impor tant to re-emphasiz e here that in order to a void an y con?ict and spur ious interr upt, it is only possib le to change the e xternal interr upt options while the i-bit is set. an y attempt to change the e xternal interr upt option while the i-bit is clear will be unsuccessful. if an e xternal interr upt is pending, it will automatically be cleared when selecting a different interrupt option. note: if the external interrupt function is disabled by the inte bit and an external interrupt is sensed b y the edge detector circuitr y , then the interr upt request is latched and the interr upt sta ys pending until the inte bit is set. the inter nal latch of the e xternal interr upt is cleared in the ?rst par t of the ser vice routine (e xcept f or the lo w le vel address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000? table 9-3 irq sensitivity intp intn irq sensitivity 0 0 negative edge and low level sensitive 0 1 negative edge only 1 0 positive edge only 1 1 positive and negative edge sensitive
motorola 9-10 mc68hc05b6 resets and interrupts 9 interr upt which is not latched); theref ore , only one e xter nal interr upt pulse can be latched during t ilil and serviced as soon as the i-bit is cleared. 9.2.3.3 timer interrupts there are ?ve different timer interr upt ?ags (icf1, icf2, ocf1, ocf2 and t of) that will cause a timer interrupt whenever they are set and enabled. these ?ve interrupt ?ags are found in the ?ve most signi?cant bits of the timer status register (tsr) at location $0013. icf1 and icf2 will v ector to the ser vice routine de?ned b y $1ff8-$1ff9, ocf1 and ocf2 will v ector to the ser vice routine de?ned by $1ff6C$1ff7 and tof will vector to the service routine de?ned by $1ff4C$1ff5 as shown in figure 5-1. there are three corresponding enab le bits; icie f or icf1 and icf2, ocie f or ocf1 and ocf2, and t oie f or t of . these enab le bits are located in the timer control register (tcr) at address $0012. see section 5.2.1 and section 5.2.2 for further information. 9.2.3.4 serial communications interface (sci) interrupts there are ?v e different interr upt ?ags (tdre, tc , or, rdrf and idle) that cause sci interr upts whenever the y are set and enab led. these ?v e interr upt ?ags are f ound in the ?v e most signi?cant bits of the sci status register (scsr) at location $0010. there are four corresponding enab le bits: tie f or tdre, tcie f or tc, rie f or or and rdrf , and ilie f or idle. these enab le bits are located in the ser ial comm unications control register 2 (sccr2) at address $000f. see section 6.11.3 and section 6.11.4. the sci interr upt causes the prog r am counter to v ector to the address pointed to b y memor y locations $1ff2 and $1ff3 which contain the star ting address of the interr upt ser vice routine . softw are in the sci interr upt ser vice routine m ust deter mine the pr ior ity and cause of the interr upt b y e xamining the interr upt ?ags and the status bits located in the ser ial comm unications status register scsr (address $0010). the gener al sequence f or clear ing an interr upt is a softw are sequence of accessing the ser ial comm unications status register while the ?ag is set f ollowed b y a read or wr ite of an associated register. refer to section 6 for a description of the sci system and its interrupts.
mc68hc05b6 motorola 9-11 resets and interrupts 9 9.2.4 hardware controlled interrupt sequence the f ollo wing three functions: reset, st op and w ait , are not in the str ictest sense interr upts . ho wever, the y are acted upon in a similar manner . flo wchar ts f or st op and w ait are sho wn in figure 2-4. reset: a reset condition causes the prog r am to v ector to its star ting address , which is contained in memor y locations $1ffe (msb) and $1fff (lsb). the i-bit in the condition code register is also set, to disable interrupts. stop: the stop instr uction causes the oscillator to be tur ned off and the processor to sleep until an external interrupt ( irq) or occurs or the device is reset. wait: the w ait instr uction causes all processor cloc ks to stop , b ut lea v es the timer cloc ks r unning. this rest state of the processor can be cleared b y reset, an external interrupt ( irq ), a timer interr upt or an sci interr upt. there are no special w ait vectors for these individual interrupts.
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mc68hc05b6 motorola 10-1 cpu core and instruction set 10 10 cpu core and instruction set this section pro vides a descr iption of the cpu core registers , the instr uction set and the addressing modes of the mc68hc05b6. 10.1 registers the mcu contains ?v e registers , as sho wn in the prog r amming model of figure 10-1. the interrupt stacking order is shown in figure 10-2. figure 10-1 programming model figure 10-2 stacking order accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 7 0 7 0 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 7 0 1 1 1 h i n z c 0 0 0 condition code register accumulator index register program counter high program counter low 7 0 stack unstack decreasing memory address increasing memory address interrupt return
motorola 10-2 mc68hc05b6 cpu core and instruction set 10 10.1.1 accumulator (a) the accum ulator is a gener al pur pose 8- bit register used to hold oper ands and results of arithmetic calculations or data manipulations. 10.1.2 index register (x) the inde x register is an 8- bit register , which can contain the inde x ed addressing v alue used to create an effective address. the index register may also be used as a temporary storage area. 10.1.3 program counter (pc) the prog r am counter is a 16- bit register , which contains the address of the ne xt b yte to be f etched. although the m68hc05 cpu core can address 64 kb ytes of memory , the actual address r ange of the mc68hc05b6 is limited to 8 kb ytes . the three most signi?cant bits of the prog ram counter are therefore not used and are permanently set to zero. 10.1.4 stack pointer (sp) the stac k pointer is a 16- bit register , which contains the address of the ne xt free location on the stack. dur ing an mcu reset or the reset stac k pointer (rsp) instr uction, the stac k pointer is set to location $00ff . the stac k pointer is then decremented as data is pushed onto the stac k and incremented as data is pulled from the stack. when accessing memor y , the ten most signi?cant bits are per manently set to 0000000011. these ten bits are appended to the six least signi?cant register bits to produce an address within the range of $00c0 to $00ff. subroutines and interrupts ma y use up to 64 (decimal) locations . if 64 locations are e xceeded, the stac k pointer wr aps around and o verwr ites the pre viously stored infor mation. a subroutine call occupies tw o locations on the stac k; an interr upt uses ?v e locations. 10.1.5 condition code register (ccr) the ccr is a 5- bit register in which f our bits are used to indicate the results of the instr uction just ex ecuted, and the ?fth bit indicates whether interr upts are mask ed. these bits can be individually tested b y a prog r am, and speci?c actions can be tak en as a result of their state . each bit is explained in the following paragraphs.
mc68hc05b6 motorola 10-3 cpu core and instruction set 10 half carry (h) this bit is set dur ing add and adc oper ations to indicate that a carr y occurred betw een bits 3 and 4. interrupt (i) when this bit is set all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last ar ithmetic , logical, or data manipulation w as z ero . carry/borrow (c) when set, this bit indicates that a carr y or borro w out of the ar ithmetic logical unit (alu) occurred dur ing the last ar ithmetic oper ation. this bit is also aff ected dur ing bit test and br anch instructions and during shifts and rotates. 10.2 instruction set the mcu has a set of 62 basic instr uctions . the y can be g rouped into ?v e diff erent types as follows: C register/memory C read/modify/write C branch C bit manipulation C control the f ollo wing par agr aphs br ie?y e xplain each type . all the instr uctions within a giv en type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in table 10-1.
motorola 10-4 mc68hc05b6 cpu core and instruction set 10 10.2.1 register/memory instructions most of these instr uctions use tw o oper ands . the ?rst oper and is either the accum ulator or the index register . the second oper and is obtained from memor y using one of the addressing modes . the jump unconditional (jmp) and jump to subroutine (jsr) instr uctions ha v e no register operand. refer to table 10-2 for a complete list of register/memory instructions. 10.2.2 branch instructions these instr uctions cause the prog r am to br anch if a par ticular condition is met; otherwise , no operation is performed. branch instructions are two-byte instructions. refer to table 10-3. 10.2.3 bit manipulation instructions the mcu can set or clear any writable bit that resides in the ?rst 256 bytes of the memory space (page 0). all por t data and data direction registers , timer and ser ial interf ace registers , control/status registers and a por tion of the on-chip ram reside in page 0. an additional f eature allo ws the softw are to test and br anch on the state of an y bit within these locations . the bit set, bit clear , bit test and br anch functions are all implemented with single instr uctions. f or the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to table 10-4. 10.2.4 read/modify/write instructions these instructions read a memory location or a register, modify or test its contents, and write the modi?ed value bac k to memor y or to the register . the test f or negativ e or z ero (tst) instr uction is an e xception to this sequence of reading, modifying and wr iting, since it does not modify the v alue. refer to table 10-5 for a complete list of read/modify/write instructions. 10.2.5 control instructions these instr uctions are register ref erence instr uctions and are used to control processor oper ation during program execution. refer to table 10-6 for a complete list of control instructions. 10.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instr uctions (see t ab le 10-7 and t ab le 10-8), and an opcode map f or the instr uction set of the m68hc05 mcu family (see table 10-9).
mc68hc05b6 motorola 10-5 cpu core and instruction set 10 table 10-1 mul instruction operation x:a ? x*a description multiplies the eight bits in the index register by the eight bits in the accum ulator and places the 16- bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 10-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b7 2 4 c7 3 5 f7 1 4 e7 2 5 d7 3 6 store x in memory stx bf 2 4 cf 3 5 ff 1 4 ef 2 5 df 3 6 add memory to a add ab 2 2 bb 2 3 cb 3 4 fb 1 3 eb 2 4 db 3 5 add memory and carry to a adc a9 2 2 b9 2 3 c9 3 4 f9 1 3 e9 2 4 d9 3 5 subtract memory sub a0 2 2 b0 2 3 c0 3 4 f0 1 3 e0 2 4 d0 3 5 subtract memory from a with borrow sbc a2 2 2 b2 2 3 c2 3 4 f2 1 3 e2 2 4 d2 3 5 and memory with a and a4 2 2 b4 2 3 c4 3 4 f4 1 3 e4 2 4 d4 3 5 or memory with a ora aa 2 2 ba 2 3 ca 3 4 fa 1 3 ea 2 4 da 3 5 exclusive or memory with a eor a8 2 2 b8 2 3 c8 3 4 f8 1 3 e8 2 4 d8 3 5 arithmetic compare a with memory cmp a1 2 2 b1 2 3 c1 3 4 f1 1 3 e1 2 4 d1 3 5 arithmetic compare x with memory cpx a3 2 2 b3 2 3 c3 3 4 f3 1 3 e3 2 4 d3 3 5 bit test memory with a (logical compare) bit a5 2 2 b5 2 3 c5 3 4 f5 1 3 e5 2 4 d5 3 5 jump unconditional jmp bc 2 2 cc 3 3 fc 1 2 ec 2 3 dc 3 4 jump to subroutine jsr bd 2 5 cd 3 6 fd 1 5 ed 2 6 dd 3 7
motorola 10-6 mc68hc05b6 cpu core and instruction set 10 table 10-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 10-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0C7) 2?n 3 5 branch if bit n is clear brclr n (n=0C7) 01+2?n 3 5 set bit n bset n (n=0C7) 10+2?n 2 5 clear bit n bclr n (n=0C7) 11+2?n 2 5
mc68hc05b6 motorola 10-7 cpu core and instruction set 10 table 10-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c 1 3 5c 1 3 3c 2 5 7c 1 5 6c 2 6 decrement dec 4a 1 3 5a 1 3 3a 2 5 7a 1 5 6a 2 6 clear clr 4f 1 3 5f 1 3 3f 2 5 7f 1 5 6f 2 6 complement com 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6 negate (twos complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6 logical shift left lsl 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst 4d 1 3 5d 1 3 3d 2 4 7d 1 4 6d 2 5 multiply mul 42 1 11 table 10-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2
motorola 10-8 mc68hc05b6 cpu core and instruction set 10 table 10-7 instruction set (1 of 2) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc ? add ? and ? ? ? asl ? ? asr ? ? bcc ? ? ? ? ? bclr ? ? ? ? ? bcs ? ? ? ? ? beq ? ? ? ? ? bhcc ? ? ? ? ? bhcs ? ? ? ? ? bhi ? ? ? ? ? bhs ? ? ? ? ? bih ? ? ? ? ? bil ? ? ? ? ? bit ? ? ? blo ? ? ? ? ? bls ? ? ? ? ? bmc ? ? ? ? ? bmi ? ? ? ? ? bms ? ? ? ? ? bne ? ? ? ? ? bpl ? ? ? ? ? bra ? ? ? ? ? brn ? ? ? ? ? brclr ? ? ? ? brset ? ? ? ? bset ? ? ? ? ? bsr ? ? ? ? ? clc ? ? ? ? 0 cli ? 0 ? ? ? clr ? ? 0 1 ? cmp ? ? condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative
mc68hc05b6 motorola 10-9 cpu core and instruction set 10 table 10-8 instruction set (2 of 2) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c com ? ? 1 cpx ? ? dec ? ? ? eor ? ? ? inc ? ? ? jmp ? ? ? ? ? jsr ? ? ? ? ? lda ? ? ? ldx ? ? ? lsl ? ? lsr ? ? 0 mul 0 ? ? ? 0 neg ? ? nop ? ? ? ? ? ora ? ? ? rol ? ? ror ? ? rsp ? ? ? ? ? rti ? ? ? ? ? rts ? ? ? ? ? sbc ? ? sec ? ? ? ? 1 sei ? 1 ? ? ? sta ? ? ? stop ? 0 ? ? ? stx ? ? ? sub ? ? swi ? 1 ? ? ? tax ? ? ? ? ? tst ? ? ? txa ? ? ? ? ? wait ? 0 ? ? ? condition code symbols h half carry (from bit 3) tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative
motorola 10-10 mc68hc05b6 cpu core and instruction set 10 table 10-9 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0 1 2 3 4 5 6 7 8 9 a b c d e f high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 5 5 3 5 3 3 6 5 9 2 3 4 5 4 3 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix 1 0001 5 5 3 6 2 3 4 5 4 3 1 0001 brclr0 bclr0 brn rts cmp cmp cmp cmp cmp cmp 3btb 2bsc 2rel 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix 2 0010 5 5 3 11 2 3 4 5 4 3 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3btb 2bsc 2rel 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix 3 0011 5 5 3 5 3 3 6 5 10 2 3 4 5 4 3 3 0011 brclr1 bclr1 bls com coma comx com com swi cpx cpx cpx cpx cpx cpx 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix 4 0100 5 5 3 5 3 3 6 5 2 3 4 5 4 3 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 2imm 2dir 3ext 3ix2 2ix1 1ix 5 0101 5 5 3 2 3 4 5 4 3 5 0101 brclr2 bclr2 bcs bit bit bit bit bit bit 3btb 2bsc 2rel 2imm 2dir 3ext 3ix2 2ix1 1ix 6 0110 5 5 3 5 3 3 6 5 2 3 4 5 4 3 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 2imm 2dir 3ext 3ix2 2ix1 1ix 7 0111 5 5 3 5 3 3 6 5 2 4 5 6 5 4 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2dir 3ext 3ix2 2ix1 1ix 8 1000 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix 9 1001 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix a 1010 5 5 3 5 3 3 6 5 2 2 3 4 5 4 3 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix b 1011 5 5 3 2 2 3 4 5 4 3 b 1011 brclr5 bclr5 bmi sei add add add add add add 3btb 2bsc 2rel 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix c 1100 5 5 3 5 3 3 6 5 2 2 3 4 3 2 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2dir 3ext 3ix2 2ix1 1ix d 1101 5 5 3 4 3 3 5 4 2 6 5 6 7 6 5 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 2rel 2dir 3ext 3ix2 2ix1 1ix e 1110 5 5 3 2 2 3 4 5 4 3 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3btb 2bsc 2rel 1inh 2imm 2dir 3ext 3ix2 2ix1 1ix f 1111 5 5 3 5 3 3 6 5 2 2 4 5 6 5 4 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3btb 2bsc 2rel 2dir 1inh 1inh 2ix1 1ix 1inh 1inh 2dir 3ext 3ix2 2ix1 1ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented
mc68hc05b6 motorola 10-11 cpu core and instruction set 10 10.3 addressing modes ten different addressing modes provide programmers with the ?exibility to optimize their code for all situations. the various indexed addressing modes make it possib le to locate data tab les, code conversion tab les and scaling tab les an ywhere in the memor y space. short index ed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or tw o b yte direct addressing instr uctions access all data b ytes in most applications . extended addressing permits jump instructions to reach all memory locations. the ter m eff ectiv e address (ea) is used in descr ibing the v ar ious addressing modes . the effectiv e address is de?ned as the address from which the argument f or an instruction is fetched or stored. the ten addressing modes of the processor are descr ibed below. p arentheses are used to indicate contents of the location or register ref erred to . f or e xample , (pc) indicates the contents of the location pointed to b y the pc (prog r am counter). an arro w indicates is replaced b y and a colon indicates concatenation of tw o b ytes . f or additional details and g raphical illustrations , ref er to the m6805 hmos/m146805 cmos f amil y micr ocomputer/ microprocessor user's manual or to the m68hc05 applications guide . 10.3.1 inherent in the inherent addressing mode , all the inf or mation necessar y to e x ecute the instr uction is contained in the opcode. operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 10.3.2 immediate in the immediate addressing mode , the oper and is contained in the b yte immediately f ollowing the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc ? pc+2 10.3.3 direct in the direct addressing mode, the effectiv e address of the argument is contained in a single b yte follo wing the opcode b yte . direct addressing allo ws the user to directly address the lo w est 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1)
motorola 10-12 mc68hc05b6 cpu core and instruction set 10 10.3.4 extended in the e xtended addressing mode , the eff ectiv e address of the argument is contained in the tw o b ytes f ollo wing the opcode b yte . instr uctions with e xtended addressing mode are capab le of referencing arguments anywhere in memory with a single three-byte instruction. when using the motorola assemb ler , the user need not specify whether an instr uction uses direct or e xtended addressing. the assembler automatically selects the short form of the instruction. ea = (pc+1):(pc+2); pc ? pc+3 address bus high ? (pc+1); address bus low ? (pc+2) 10.3.5 indexed, no offset in the index ed, no offset addressing mode , the effectiv e address of the argument is contained in the 8-bit index register. this addressing mode can access the ?rst 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc ? pc+1 address bus high ? 0; address bus low ? x 10.3.6 indexed, 8-bit offset in the inde x ed, 8-bit offset addressing mode , the eff ectiv e address is the sum of the contents of the unsigned 8-bit inde x register and the unsigned b yte f ollo wing the opcode . theref ore the oper and can be located an ywhere within the lo w est 511 memor y locations . this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc ? pc+2 address bus high ? k; address bus low ? x+(pc+1) where k = the carry from the addition of x and (pc+1) 10.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit inde x register and the tw o unsigned bytes following the opcode. this address mode can be used in a manner similar to inde x ed, 8-bit offset e xcept that this three-b yte instr uction allows tab les to be an ywhere in memor y . as with direct and e xtended addressing, the motorola assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc ? pc+3 address bus high ? (pc+1)+k; address bus low ? x+(pc+2) where k = the carry from the addition of x and (pc+2)
mc68hc05b6 motorola 10-13 cpu core and instruction set 10 10.3.8 relative the relativ e addressing mode is only used in br anch instr uctions . in relativ e addressing, the contents of the 8-bit signed b yte (the offset) f ollo wing the opcode are added to the pc if , and only if, the br anch conditions are tr ue. otherwise , control proceeds to the ne xt instr uction. the span of relativ e addressing is from C126 to +129 from the opcode address . the prog r ammer need not calculate the offset when using the motorola assemb ler , since it calculates the proper offset and checks to see that it is within the span of the branch. ea = pc+2+(pc+1); pc ? ea if branch taken; otherwise ea = pc ? pc+2 10.3.9 bit set/clear in the bit set/clear addressing mode , the bit to be set or cleared is par t of the opcode . the b yte follo wing the opcode speci?es the address of the b yte in which the speci?ed bit is to be set or cleared. any read/wr ite bit in the ?rst 256 locations of memor y , including i/o , can be selectiv ely set or cleared with a single two-byte instruction. ea = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) 10.3.10 bit test and branch the bit test and br anch addressing mode is a combination of direct addressing and relativ e addressing. the bit to be tested and its condition (set or clear) is included in the opcode . the address of the b yte to be tested is in the single b yte immediately follo wing the opcode b yte (ea1). the signed relative 8-bit offset in the third b yte (ea2) is added to the pc if the speci?ed bit is set or cleared in the speci?ed memor y location. this single three-byte instruction allows the program to br anch based on the condition of an y readab le bit in the ?rst 256 locations of memor y . the span of br anch is from C125 to +130 from the opcode address . the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc ? pc+2 address bus high ? 0; address bus low ? (pc+1) ea2 = pc+3+(pc+2); pc ? ea2 if branch taken; otherwise pc ? pc+3
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mc68hc05b6 motorola 11-1 electrical specifications 11 11 electrical specifications this section contains the electr ical speci?cations and associated timing inf or mation f or the mc68hc05b6. 11.1 maximum ratings note: this de vice contains circuitr y designed to protect against damage due to high electrostatic v oltages or electr ic ?elds . ho wever , it is recommended that nor mal precautions be tak en to a v oid the application of an y v oltages higher than those giv en in the maximum ratings tab le to this high impedance circuit. f or maximum reliability all unused inputs should be tied to either v ss or v dd . (1) all voltages are with respect to v ss . (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. table 11-1 maximum ratings rating symbol value unit supply voltage (1) v dd C 0.5 to +7.0 v input voltage v in v ss C 0.5 to v dd + 0.5 v input voltage C self-check mode ( irq pin only) v in v ss C 0.5 to 2v dd + 0.5 v operating temperature range C standard (mc68hc05b6) C extended (mc68hc05b6c) C automotive (mc68hc05b6m) t a t l to t h 0 to +70 C40 to +85 C40 to +125 ?c storage temperature range t stg C 65 to +150 ?c current dr ain per pin (e xcluding vdd and vss) (2) C source C sink i d i s 25 45 ma ma
motorola 11-2 mc68hc05b6 electrical specifications 11 11.2 thermal characteristics and power considerations the average chip junction temperature, t j , in degrees celsius can be obtained from the following equation: [1] where: t a = ambient temperature (?c) q ja = package thermal resistance, junction-to-ambient (?c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ? v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [2] solving equations [1] and [2] for k gives: [3] where k is a constant f or a particular par t. k can be deter mined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table 11-2. table 11-2 package thermal characteristics characteristics symbol value unit thermal resistance C 64-pin quad ?at package q ja 50 ?c/w C plastic 56 pin shrink dil package q ja 50 ?c/w C plastic 52 pin plcc package q ja 50 ?c/w figure 11-1 equivalent test load t j t a p d q ja ( ) + = p d k t j 273 + --------------------- = k p d t a 273 + ( ) q ja p d 2 + = voltage pins r1 r2 c 4.5v pa0C7, pb0C7, pc0C7 3.26 k? 2.38 k? 50 pf 3.0v pa0C7, pb0C7, pc0C7 10.91 k? 6.32 k? 50 pf v dd = 4.5/3.0 v r2 r1 c test point
mc68hc05b6 motorola 11-3 electrical specifications 11 11.3 dc electrical characteristics (1) all i dd measurements taken with suitab le decoupling capacitors across the po w er supply to suppress the tr ansient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an external square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. table 11-3 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.8 v dd C 0.8 v dd C 0.4 v dd C 0.4 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.1 0.4 0.4 1 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (extended) C 40 to 125 (automotive) i dd 3.5 0.5 1 0.35 2 6 1.5 2 1 10 20 60 60 ma ma ma ma a a a a high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 0.2 1 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, i in 5 a capacitance ports (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c in c in c in 12 22 12 8 tbd tbd pf pf pf pf
motorola 11-4 mc68hc05b6 electrical specifications 11 11.3.1 i dd trends for 5v operation figure 11-2 run i dd vs internal operating frequency (4.5v, 5.5v) figure 11-3 run i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v) figure 11-4 wait i dd vs internal operating frequency (4.5v, 5.5v) 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 i dd (ma) internal operating frequency (mhz) 5.5 v 4.5 v 1.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 i dd (ma) internal operating frequency (mhz) 5.5 v 4.5 v 1 0.8 0.6 0.4 0.2 2.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 i dd (ma) internal operating frequency (mhz) 5.5 v 4.5 v 2 1.5 1 0.5
mc68hc05b6 motorola 11-5 electrical specifications 11 figure 11-5 wait i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v) figure 11-6 increase in i dd vs frequency f or a/d , sci systems activ e , vdd = 5.5 v figure 11-7 i dd vs mode vs internal operating frequency, v dd = 5.5v 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 i dd (ma) internal operating frequency (mhz) 5.5 v 4.5 v 0.9 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 i dd (ma) internal operating frequency (mhz) a/d + sci a/d 1.6 sci 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 i dd (ma) internal operating frequency (mhz) wait i dd (sm = 1) run i dd wait i dd run i dd (sm = 1)
motorola 11-6 mc68hc05b6 electrical specifications 11 (1) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an e xternal square-wave clock source (f osc = 2.1 mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all por ts con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. table 11-4 dc electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.2 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 0.4 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.3 v dd C 0.3 v dd C 0.1 v dd C 0.1 v output low voltage (i load = 0.4 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 0.4 ma) reset v ol v ol 0.1 0.2 0.3 0.6 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (extended) C 40 to 125 (automotive) i dd 1.2 0.2 0.4 0.15 1 3 1 1.5 0.5 10 10 40 40 ma ma ma ma a a a a high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 0.2 1 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, i in 5 a capacitance por ts (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c in c in c in 12 22 12 8 tbd tbd pf pf pf pf
mc68hc05b6 motorola 11-7 electrical specifications 11 11.3.2 i dd trends for 3.3v operation figure 11-8 run i dd vs internal operating frequency (3 v, 3.6v) figure 11-9 run i dd (sm = 1) vs internal operating frequency (3v,3.6v) figure 11-10 wait i dd vs internal operating frequency (3v, 3.6v) 2.5 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) 3.6 v 3.0 v 2 1.5 1 0.5 0.6 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) 3.6 v 3.0 v 0.5 0.4 0.3 0.2 0.1 1.2 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) 3.6 v 3.0 v 1 0.8 0.6 0.4 0.2
motorola 11-8 mc68hc05b6 electrical specifications 11 figure 11-11 wait i dd (sm = 1) vs internal operating frequency (3v, 3.6v) figure 11-12 increase in i dd vs frequency f or a/d , sci systems activ e , v dd = 3.6 v figure 11-13 i dd vs mode vs internal operating frequency, v dd = 3.6v 0.5 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) 3.6 v 3.0 v 0.4 0.3 0.2 0.1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) a/d sci a/d + sci 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 i dd (ma) internal operating frequency (mhz) run i dd wait i dd run i dd (sm = 1) wait i dd (sm = 1)
mc68hc05b6 motorola 11-9 electrical specifications 11 11.4 a/d converter characteristics (1) performance veri?ed down to 2.5v ?vr, b ut accuracy is tested and guaranteed at ?vr = 5v10%. (2) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table 11-5 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 1 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r (1) minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (3) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
motorola 11-10 mc68hc05b6 electrical specifications 11 (1) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table 11-6 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 1 lsb quantization error uncertainty due to converter resolution 1 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 2 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion internal rc oscillator 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling internal rc oscillator (1) 12 s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (2) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
mc68hc05b6 motorola 11-11 electrical specifications 11 11.5 control timing (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table 11-7 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc dc 2.1 2.1 mhz mhz cycle time (see figure 9-1) t cyc 480 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 100 ms a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 125 (automotive) t era t era t era 10 10 10 ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 125 (automotive) t prog t prog t prog 10 10 20 ms ms ms timer (see figure 11-14) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 125 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 90 ns
motorola 11-12 mc68hc05b6 electrical specifications 11 (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table 11-8 control timing for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 1.0 1.0 mhz mhz cycle time (see figure 9-1) t cyc 1000 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 100 ms a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 125 (automotive) t era t era t era 30 30 30 ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 125 (automotive) t prog t prog t prog 30 30 30 ms ms ms timer (see figure 11-14) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 250 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 200 ns
mc68hc05b6 motorola 11-13 electrical specifications 11 figure 11-14 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
motorola 11-14 mc68hc05b6 electrical specifications this page intentionally left blank 11
mc68hc05b6 motorola 12-1 mechanical data 12 12 mechanical data 12.1 mc68hc05b6 pin con?gurations 12.1.1 52-pin plastic leaded chip carrier (plcc) figure 12-1 52-pin plcc pinout pc3 pc4 pc5 pc6 pc7 vss vpp1 pb0 pb1 pb2 pb3 pb4 pb5 vrh pd4/an4 vdd pd3/an3 pd2/an2 pd1/an1 pd0/an0 nc osc1 osc2 reset irq plma plmb tcap1 tcap2 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 vrl nc pd5/an5 pd6/an6 pd7/an7 tcmp1 tcmp2 tdo sclk rdi pc0 pc1 pc2/eclk 46 45 44 43 42 41 40 39 38 37 36 35 34 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47
motorola 12-2 mc68hc05b6 mechanical data 12 12.1.2 64-pin quad ?at pack (qfp) figure 12-2 64-pin qfp pinout nc pb0 nc vpp1 17 18 20 21 22 23 24 25 26 27 29 30 31 32 19 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 46 pb6 pb7 nc pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 nc tcap2 tcap1 plmb d/a nc pc1 pc0 nc nc nc nc rdi sclk tdo tcmp2 tcmp1 pd7/an7 pd6/an6 pd5/an5 nc nc vrl vrh vdd pd3/an3 pd2/an2 pd1/an1 nc nc nc osc1 osc2 reset irq plma d/a pd4/an4 pc2/eclk pc3 pc5 pc6 pc7 vss pb1 pb2 pb3 pb4 pb5 pc4 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 pd0/an0 28 64 63 61 60 59 58 56 55 54 53 52 51 50 49 62 57 device pin 27 pin 57 mc68hc05b4 nc nc mc68hc05b6 mc68hc05b8 mc68hc05b16 mc68hc05b32 nc vpp1 mc68hc705b5 not available in this package mc68hc705b16 vpp6 vpp1 mc68hc705b32 vpp6 vpp1
mc68hc05b6 motorola 12-3 mechanical data 12 12.1.3 56-pin shrink dual in line package (sdip) figure 12-3 56-pin sdip pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tcmp1 pd7 pd6 pd5 nc nc nc vrl vrh pd4 vdd pd3 pd2 pd1 pd0 nc osc1 osc2 reset irq plma 22 23 24 25 26 27 28 56 tcmp2 tdo sclk rdi pc0 pc1 nc pc2 pc3 pc4 pc5 pc6 pc7 vss vpp1 pb0 pb1 pb2 pb3 pb4 pb5 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 plmb tcap1 tcap2 pa7 pa6 pa5 pa4 nc pb6 pb7 pa0 pa1 pa2 pa3 device pin 16 pin 42 mc68hc05b4 nc nc mc68hc05b6 nc vpp1 mc68hc05b8 nc vpp1 mc68hc05b16 nc vpp1 mc68hc05b32 nc vpp1 mc68hc705b5 vpp nc mc68hc705b32 vpp6 vpp1
motorola 12-4 mc68hc05b6 mechanical data 12 12.2 mc68hc05b6 mechanical dimensions 12.2.1 52-pin plastic leaded chip carrier (plcc) figure 12-4 52-pin plcc mechanical dimensions ClC CmC CpC CnC pin 1 pin 52 v w y brk z r a c j e g g1 u b g1 z1 x 0.10 CtC seating plane 0.18 t n Cp l Cm m s s s s case no. 778-02 52 lead plcc w/o pedestal dim. min. max. notes dim. min. max. a 19.94 20.19 1. datums ClC, CmC, CnC and CpC are deter mined where top of lead shoulder exits plastic body at mould parting line. 2. dimension g1, tr ue position to be measured at datum CtC (seating plane). 3. dimensions r and u do not include mould protrusion. allowable mould protrusion is 0.25 mm per side. 4. dimensions and tolerancing per ansi y 14.5m, 1982. 5. all dimensions in mm. u 19.05 19.20 b 19.94 20.19 v 1.07 1.21 c 4.20 4.57 w 1.07 1.21 e 2.29 2.79 x 1.07 1.42 f 0.33 0.48 y 0.50 g 1.27 bsc z 2 10 h 0.66 0.81 g1 18.04 18.54 j 0.51 k1 1.02 k 0.64 z1 2 10 r 19.05 19.20 0.18 t l Cm n Cp m s s s s 0.18 t l Cm n Cp m s s s s 0.18 t n Cp l Cm m s s s s 0.25 t l Cm n Cp s s s s s
mc68hc05b6 motorola 12-5 mechanical data 12 12.2.2 64-pin quad ?at pack (qfp) figure 12-5 64-pin qfp mechanical dimensions 64 lead qfp 0.20 m c a C b s d s l 33 48 16 1 32 17 49 64 - b - b v 0.05 a C b - d - a s 0.20 m h a C b s d s l - a - detail a b b - a, b, d - p detail a f n j d section bCb base metal g h e c -c- m detail c m -h- datum plane seating plane u t r q k w x dim. min. max. notes dim. min. max. a 13.90 14.10 1. datum plane ChC is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. datums aCb and Cd to be determined at datum plane ChC. 3. dimensions s and v to be determined at seating plane CcC. 4. dimensions a and b do not include mould protrusion. allowable mould protrusion is 0.25 mm per side. dimensions a and b do include mould mismatch and are determined at datum plane ChC. 5. dimension d does not include dambar protrusion. allowable dambar protr usion shall be 0.08 total in e xcess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 6. dimensions and tolerancing per ansi y 14.5m, 1982. 7. all dimensions in mm. m 5 10 b 13.90 14.10 n 0.130 0.170 c 2.067 2.457 p 0.40 bsc d 0.30 0.45 q 2 8 e 2.00 2.40 r 0.13 0.30 f 0.30 s 16.20 16.60 g 0.80 bsc t 0.20 ref h 0.067 0.250 u 9 15 j 0.130 0.230 v 16.20 16.60 k 0.50 0.66 w 0.042 nom l 12.00 ref x 1.10 1.30 0.20 m c a C b s d s 0.05 a C b 0.20 m h a C b s d s 0.20 m c a C b s d s case no. 840c
motorola 12-6 mc68hc05b6 mechanical data 12 12.2.3 56-pin shrink dual in line package (sdip) figure 12-6 56-pin sdip mechanical dimensions 1 28 56 29 - a - n g d f l m plane seating c dim. min. max. notes dim. min. max. a 51.69 52.45 1. due to space limitations, this case shall be represented by a general case outline, rather than one showing all the leads. 2. dimensions and tolerancing per ansi y 14.5 1982. 3. all dimensions in mm. 4. dimension l to centre of lead when formed parallel. 5. dimensions a and b do not include mould ?ash. allowable mould ?ash is 0.25 mm. h 7.62 bsc b 13.72 14.22 j 0.20 0.38 c 3.94 5.08 k 2.92 3.43 d 0.36 0.56 l 15.24 bsc e 0.89 bsc m 0? 15? f 0.81 1.17 n 0.51 1.02 g 1.778 bsc case no. 859-01 56 lead sdip - b - h k - t - 0.25 t a m s 0.25 t b m s j e
mc68hc05b6 motorola 13-1 ordering information 13 13 ordering information this section descr ibes the inf or mation needed to order the mc68hc05b6 and other f amily members . t o initiate a r om patter n f or the mcu , it is necessar y to contact y our local ?eld ser vice of?ce , local sales person or motorola representativ e . please note that y ou will need to supply details such as: mask option selections; temper ature r ange; oscillator frequency; pac kage type; electr ical test requirements; and de vice mar king details so that an order can be processed, and a customer speci?c part n umber allocated. ref er to t ab le 13-1 f or appropriate part numbers . the par t number consists of the de vice title plus the appropr iate suf?x. f or example , the mc68hc05b6 in 52-pin plcc package at C40 to +85?c would be ordered as: mc68hc05b6cfn. table 13-1 mc order numbers device title package type suf?x 0 to 70?c suf?x -40 to +85?c suf?x -40 to +105?c suf?x -40 to +125?c mc68hc05b6 52-pin plcc fn cfn n/a mfn 64-pin qfp fu cfu n/a mfu 56-pin sdip b cb n/a mb mc68hc05b4 52-pin plcc fn cfn n/a mfn 56-pin sdip b cb n/a mb mc68hc05b8 52-pin plcc fn cfn n/a mfn 64-pin qfp fu cfu n/a mfu 56-pin sdip b cb n/a mb mc68hc05b16 52-pin plcc fn cfn vfn n/a 64-pin qfp fu cfu vfu n/a 56-pin sdip b cb vb n/a mc68hc05b32 52-pin plcc fn n/a vfn n/a 64-pin qfp fu n/a vfu n/a 56-pin sdip b n/a vb n/a mc68hc705b5 52-pin plcc fn cfn vfn mfn 56-pin sdip b cb vb mb mc68hc705b16 52-pin plcc fn cfn vfn n/a 64-pin qfp fu cfu vfu n/a mc68hc705b32 52-pin plcc fn n/a vfn n/a 64-pin qfp fu n/a vfu n/a 56-pin sdip b n/a vb n/a
motorola 13-2 mc68hc05b6 ordering information 13 13.1 eproms f or the mc68hc05b6, an 8 kb yte epr om prog r ammed with the customer s softw are (positiv e logic f or address and data) should be submitted f or pattern gener ation. all un used bytes should be progr ammed to $00. the siz e of epr om which should be used f or all other f amily members is listed in table 13-2. the eprom should be clearly labelled, placed in a conductive ic carrier and securely packed. 13.2 veri?cation media all or iginal patter n media (epr oms) are ?led f or contr actual pur poses and are not retur ned. a computer listing of the r om code will be gener ated and retur ned with a listing v eri?cation form. the listing should be thoroughly chec k ed and the v er i?cation f or m completed, signed and retur ned to motorola. the signed v eri?cation for m constitutes the contr actual agreement f or creation of the custom mask. if desired, motorola will prog ram blank epr oms (supplied b y the customer) from the data ?le used to create the custom mask, to aid in the veri?cation process. 13.3 rom veri?cation units (rvu) t en mcus containing the customer s rom patter n will be pro vided for program veri?cation. these units will ha v e been made using the custom mask b ut are f or r om v er i?cation only . f or expediency , the y are usually unmar k ed and are tested only at room temper ature (25 ?c) and at 5 volts . these r vus are included in the mask charge and are not production par ts . the y are neither backed nor guaranteed by motorola quality assurance. table 13-2 eproms for pattern generation device size of eprom mc68hc05b4 8 kbyte mc68hc05b8 8 kbyte mc68hc05b16 16 kbyte mc68hc05b32 32 kbyte
mc68hc05b6 motorola a-1 mc68hc05b4 14 a mc68hc05b4 the mc68hc05b4 is a de vice similar to the mc68hc05b6, b ut without eepr om and ha ving a reduced rom siz e of 4 kb ytes . the entire mc68hc05b6 data sheet applies to the mc68hc05b4, with the exceptions outlined in this appendix. features ? 4158 bytes user rom (including 14 bytes user vectors) ? no eeprom section 3.5, eepr om, theref ore , does not apply to the mc68hc05b4, and the register at address $07 only allo ws the user to select whether or not the eclk should appear at pc2, using bit 3 of $07. all other bits of this register read as 0.
motorola a-2 mc68hc05b4 mc68hc05b4 14 figure a-1 mc68hc05b4 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 4158 bytes self check rom (including 14 bytes user vectors)
mc68hc05b6 motorola a-3 mc68hc05b4 14 figure a-2 memory map of the mc68hc05b4 user vectors (14 bytes) $1ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (4096 bytes) self-check rom ii (240 bytes) $0800 reserved mc68hc05b4 registers $1ff4C5 $1ff6C7 $1ff8C9 $1ffaCb $1ffcCd $1ffeCf
motorola a-4 mc68hc05b4 mc68hc05b4 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. table a-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7/ an7 pd6/ an6 pd5/ an5 pd4/ an4 pd3/ an3 pd2/ an2 pd1/ an1 pd0/ an0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eclk control $0007 0 0 0 0 eclk 0 0 0 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl uuuu uuuu sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 uuuu uuuu input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned
mc68hc05b6 motorola b-1 mc68hc05b8 14 b mc68hc05b8 the mc68hc05b8 is a de vice similar to the mc68hc05b6, b ut with an increased r om size of 7.25 kb ytes . the entire mc68hc05b6 data sheet applies to the mc68hc05b8, with the exceptions outlined in this appendix. features ? 7230 bytes user rom (including 14 bytes user vectors)
motorola b-2 mc68hc05b8 mc68hc05b8 14 figure b-1 mc68hc05b8 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 7230 bytes self check rom (including 14 bytes user vectors)
mc68hc05b6 motorola b-3 mc68hc05b8 14 figure b-2 memory map of the mc68hc05b8 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (7168 bytes) self-check rom ii (240 bytes) $0300 optr (1 byte) non protected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b8 registers user vectors (14 bytes) $1ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff4C5 $1ff6C7 $1ff8C9 $1ffaCb $1ffcCd $1ffeCf
motorola b-4 mc68hc05b8 mc68hc05b8 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=w atchdog enab led, 0=w atchdog disab led. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. table b-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected
mc68hc05b6 motorola c-1 mc68hc705b5 14 c mc68hc705b5 the mc68hc705b5 is a de vice similar to the mc68hc05b6, b ut with the 6 kb ytes rom and 256 bytes eeprom replaced by a single eprom array . in addition, the self-chec k routines available on the mc68hc05b6 are replaced b y bootstr ap ?r mware . the mc68hc705b5 is intended to oper ate as a one time prog rammable (otp) v ersion of the mc68hc05b6 or the mc68hc05b4, meaning that the application prog r am can ne v er be er ased once it has been loaded into the epr om. the entire mc68hc05b6 data sheet applies to the mc68hc705b5, with the e xceptions outlined in this appendix. features ? 6206 bytes eprom (including 14 bytes user vectors) ? no eeprom ? bootstrap ?rmware ? simultaneous programming of up to 4 bytes ? data protection for program code ? optional pull-down resistors on port b and port c ? additional temperature range available; -40 to +105?c ? mc68hc05b6 mask options are programmable using control bits held in the options register
motorola c-2 mc68hc05b6 mc68hc705b5 14 figure c-1 mc68hc705b5 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp6 256 bytes eprom1 6206 bytes 2 / 32 plma d/a plmb d/a 8-bit 496 bytes bootstrap rom eprom (including 14 bytes user vectors)
mc68hc05b6 motorola c-3 mc68hc705b5 14 figure c-2 memory map of the mc68hc705b5 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $0300 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user eprom (48 bytes) bootstrap rom i (256 bytes) user eprom (5888 bytes) bootstrap rom ii (240 bytes) $0800 user eprom 1 (256 bytes) $1efe options register reserved mc68hc705b5 registers options register $1efe user vectors (14 bytes) $1ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff2C3 $1ff2C3 $1ff2C3 $1ff2C3 $1ff2C3 $1ff2C3
motorola c-4 mc68hc05b6 mc68hc705b5 14 (1) this bit re?ects the state of the epp bit in the options register ($1efe) at reset. (2) this bit is set each time the device is powered-on. (3) the state of the wdog bit after reset depends on the mask option selected; 1 = watchdog enabled and 0 = watchdog disabled. (4) because this register is implemented in eprom, reset has no effect on the state of the individual bits. table c-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eclk control $0007 eppt (1) elat epgm eclk u?00 0uuu a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (2) intp intn inte sfa sfb sm wdog (3) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl uuuu sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 uuuu input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (4) $1efe epp 0 rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola c-5 mc68hc705b5 14 c.1 eprom the mc68hc705b5 has a total of 6206 b ytes of epr om, 256 b ytes being reser v ed f or the eprom1 arra y (see figure c-2). the epp bit (epr om protect) is not operative on the eprom1 array , making it possib le to prog r am it after the main epr om has been prog r ammed and protected. the reset and interr upt v ectors are located at $1ff2-$1fff and the epr om control register described in section c.2.1 is located at address $0007. the eprom arra y is supplied b y the vpp6 pin in both read and prog ramming modes. typically the users softw are will be loaded in a prog r amming board where vpp6 is controlled b y one of the bootstr ap loader routines (bootloader mode). it will then be placed in an application where no programming occurs (user mode). in this case the vpp6 pin should be hardwired to v dd . an erased eprom byte reads as $00. warning: a minim um v dd v oltage m ust be applied to the vpp6 pin at all times , including power-on, as a lower voltage could damage the device. c.1.1 eprom programming operation the user prog r am can be used to prog r am some epr om locations , pro vided the proper procedure is followed. in particular, the programming sequence must be r unning in ram, as the epr om will not be a vailab le f or code e x ecution while the ela t bit is set. the vpp6 s witching m ust occur externally , after the epgm bit is set, f or example , under the control of a signal gener ated on a pin by the programming routine. note: when the par t becomes a pr om, only the cum ulative progr amming of bits to logic 1 is possible if multiple programming is made on the same byte. t o allo w sim ultaneous prog r amming of up to 4 b ytes , the y m ust be in the same g roup of addresses which share the same most signi?cant address bits; only the two lsbs can change.
motorola c-6 mc68hc05b6 mc68hc705b5 14 c.2 eprom registers c.2.1 eprom control register bit 7 factory use only this bit is strictly for factory use only and will always read zero. eppt eprom protect test bit this bit is a cop y of the epr om protect bit (epp) located in the option register . when ela t is set, the eppt bit can be tested b y the software to chec k if the epr om arra y is protected or not, since the eprom content is not available when elat is set. por or external reset modi?es this bit to re?ect the state of the epp bit in the options register. elat eprom programming latch enable bit 1 (set) C when set, this bit allows latching of the address and up to 4 data bytes for further programming, provided epgm is zero. 0 (clear) C when cleared, program and interrupt routines can be executed and data can be read in the eprom or ?rmware rom. stop, power-on and external reset clear this bit. epgm eprom programming bit this bit is the epr om program enab le bit. it can be set to 1 to enab le progr amming only after ela t is set and at least one b yte is wr itten to the epr om. it is not possib le to clear epgm b y software, but clearing elat will always clear epgm. eclk external clock option bit see section 4.3. (1) this bit is a copy of the epp bit in the options register at $1efe and therefore its state on reset will be the same as that for the epp bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eclk control $0007 eppt (1) elat epgm eclk u?00 0uuu
mc68hc05b6 motorola c-7 mc68hc705b5 14 c.3 options register (optr) note: this register can only be written to while the device is in bootloader mode. bit 7 factory use only warning: this bit is str ictly f or f actor y use only and will alw a ys read z ero to a v oid accidental damage to the device. any attempt to write to this bit could result in physical damage. epp eprom protect this bit protects the contents of the main epr om against accidental modi?cation; it has no eff ect on reading or executing code in the eprom. 1 (set) C eprom contents are protected. 0 (clear) C eprom contents are not protected. rtim reset time this bit can modify t porl , i.e. the time that the reset pin is kept low following a power-on reset. this feature is handled in the rom part via a mask option. 1 (set) C t porl = 16 cycles. 0 (clear) C t porl = 4064 cycles. rwat watchdog after reset this bit can modify the status of the watchdog counter after reset. 1 (set) C the watchdog will be active immediately following power-om or external reset (except in bootstrap mode). 0 (clear) C the watchdog system will be disabled after power-on or external reset. wwat watchdog during wait mode this bit can modify the status of the watchdog counter during wait mode. (1) this register is implemented in eprom, therefore reset has no effect on the state of the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) $1efe epp 0 rtim rwat wwat pbpd pcpd not affected
motorola c-8 mc68hc05b6 mc68hc705b5 14 1 (set) C the watchdog will be active during wait mode. 0 (clear) C the watchdog system will be disabled during wait mode. pbpd C port b pull-down resistors 1 (set) C pull-down resistors are connected to all 8 pins of port b; the pull-down, r pd , is active only while the pin is an input. 0 (clear) C no pull-down resistors are connected. pcpd port c pull-down resistors 1 (set) C pull-down resistors are connected to all 8 pins of port c; the pull-down, r pd , is active only while the pin is an input. 0 (clear) C no pull-down resistors are connected. the combination of bit 0 and bit 1 allo ws the option of pull-do wn resistors on 0, 8 or 16 inputs . this feature is not available on the mc68hc05b6. c.4 bootstrap mode the 432 b ytes of self-chec k ?r mw are on the mc68hc05b6 are replaced with 496 b ytes of bootstr ap ?r mware . the bootstr ap ?r mw are located from $0200 to $02ff and $1f00 to $1fef can be used to prog r am the epr om, to chec k if the epr om is er ased and to load and e xecute data in ram. when the mc68hc705b5 is placed in the bootstr ap mode , the bootstr ap reset v ector is f etched and the bootstr ap ?r mw are star ts to e xecute . t ab le c-2 sho ws the conditions required to enter each level of bootstr ap mode on the r ising edge of reset . the hold time on the irq and tcap1 pins after the external reset pin is brought high is two clock cycles. table c-2 mode of operation selection irq pin tcap1 pin pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x single chip + 9 volts v dd 0 1 0 erased eprom veri?cation + 9 volts v dd x 0 0 eprom parallel bootstrap load + 9 volts v dd x 1 1 eprom (ram) serial bootstrap load and execute + 9 volts v dd x 0 1 ram parallel bootstrap load and execute x = dont care
mc68hc05b6 motorola c-9 mc68hc705b5 14 the bootstrap program ?rst copies par t of itself into ram, as the prog ram cannot be executed in r om dur ing v eri?cation/progr amming of the epr om. it then sets the tcmp1 output to a logic high level. figure c-3 modes of operation ?ow chart (1 of 2) tcap1 set? irq at 9v? eprom erased? pd2 set? pd3 set? pd4 set? reset program eprom; parallel load; green led ?ashes programming ok? user mode red led on green led on non-user mode red led on green led on non-user mode a y y y y y y n n n n n n y bootstrap mode eprom not erased eprom veri?ed parallel eprom bootstrap bad eprom programming n
motorola c-10 mc68hc05b6 mc68hc705b5 14 figure c-4 modes of operation ?ow chart (2 of 2) programming ok? negative address? pd4 set? pd3 set? transmit last four programmed locations a red led off receive address receive four data execute ram program at $0083 green led on load next ram byte ram full? execute ram program at $0050 program eprom data at address; green led ?ashes red led on n y y y y y n n n serial eprom (ram) bootstrap bad eprom bootstrap ram programming n
mc68hc05b6 motorola c-11 mc68hc705b5 14 c.4.1 erased eprom veri?cation the ?owchar t in figure c-3 and figure c-4 sho ws that the on-chip bootstr ap routines can be used to chec k if the epr om is er ased (all $00s). if a non $00 b yte is detected, the red led sta ys on and the routine will stay in a loop. only when the whole eprom content is veri?ed as erased will the green led be turned on. c.4.2 eprom parallel bootstrap load when this mode is selected, the epr om is loaded in increasing address order with non epr om segments being skipped b y the loader. simultaneous programming is performed by reading four b ytes of data bef ore actual prog r amming is perf or med, thus dividing the loading time of the inter nal eprom by four. when pd2=0, the progr amming time is set to 5 milliseconds and the prog ram/verify routine takes approximately 15 seconds. par allel data is entered through p or t a, while the 13-bit address is output on por t b and pc0 to pc4. if the data comes from an e xternal eprom, the handshake can be disabled by connecting together pc5 and pc6. if the data is supplied via a par allel interface , handshaking will be pro vided by pc5 and pc6 according to the timing diagram of figure c-5. during programming, the green led ?ashes at about 3 hz. upon completion of the prog r amming oper ation, the epr om content is chec k ed against the exter nal data source . if prog r amming is v er i?ed the g reen led sta ys on, while an error causes the red led to be turned on. figure c-6 shows a circuit that can be used to program the eprom (or to load and execute data in the ram). note: the entire epr om can be loaded from the e xter nal source; if it is desired to lea ve a segment undisturbed, the data for this segment should be all zeros. figure c-5 timing diagram with handshake data read data read address hdsk out (pc5) data hdsk in (pc6) f29
motorola c-12 mc68hc05b6 mc68hc705b5 14 figure c-6 eprom(ram) parallel bootstrap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe vcc pgm vpp 14 22 10 9 8 7 6 5 4 1 26 27 28 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100f 22pf 4.0 mhz 1n914 1k? 1.0f 22pf 10m? 100k? 1n914 reset run 0.01f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 nc 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k? nc tcmp1 tcmp2 plma plmb 470? 470? red led green led 4k7? 4k7? 12 k? bc239c bc309c 10k ? 27c64 + + vrh red led programming failed green led programming ok 25 1nf 1n5819 1 k? + ram eprom 47f + 20 mc68hc705b5
mc68hc05b6 motorola c-13 mc68hc705b5 14 c.4.3 eprom (ram) serial bootstrap load and execute the serial routine communicates through the sci with an external host, typically a pc, by means of an rs232 link at 9600 baud, 8-bit, no parity and full duplex. data for mat is not ascii, b ut 8-bit binary , so a complementar y program must be run by the host to supply the required format. such a program is available for the ibm pc from motorola. the eprom bootstr ap routines are used to customise the o tp eprom. t o increase the speed of prog r amming, f our b ytes are prog r ammed in par allel while the data is sim ultaneously transmitted and receiv ed in full duple x. this implies that while 4 b ytes are being prog rammed, the ne xt 4 b ytes are receiv ed and the preceding 4 b ytes are echoed. the f or mat accepted b y the ser ial loader is as follows: [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] address n m ust ha v e the tw o lsbs at z ero so that n, n+1, n+2 and n+3 ha v e identical msbs . these bloc ks of f our b ytes do not need to be contiguous , as a ne w address is tr ansmitted for each new group. the protocol is as follows: 1 the mc68hc705b5 sends the last tw o bytes progr ammed to the host as a prompt; this allows veri?cation by the host of proper programming. 2 in response to the ?rst byte prompt, the host sends the ?rst address byte. 3 after receiving the ?rst address byte, the mc68hc705b5 sends the next byte programmed. 4 the exchange of data contin ues until the mc68hc705b5 has sent the f our data b ytes and the host has sent the 2 address data b ytes and 4 data b ytes. 5 if the data is non zero, it is programmed at the address provided, while the next address and bytes are received and the previous data is echoed. 6 loop to 1. after reset, the mc68hc705b5 ser ial bootstr ap routine will ?rst echo tw o bloc ks of f our bytes at $0000, as no data is programmed yet. if the data sent in is $00, no prog r amming in the epr om tak es place , and the contents of the accessed location are retur ned as a prompt. the entire epr om memor y can be read in this fashion (serial dump). the red led will be on if the data read from the eprom is not $00. serial ram loading and execute can be accomplished in this mode. a ram byte will be written if the address sent by the host in the serial protocol points to the ram. in the ram bootloader mode , all interr upt v ectors are mapped to pseudo-v ectors in ram (see tab le c-3). this allo ws prog r ammers to use their o wn ser vice-routine addresses . each pseudo-v ector is allo w ed three b ytes of space r ather than the tw o b ytes f or nor mal v ectors, because an e xplicit jump (jmp) opcode is needed to cause the desired jump to the user s service-routine address.
motorola c-14 mc68hc05b6 mc68hc705b5 14 a 10-byte stac k is also reser v ed at the top of the ram allo wing, for example , one interr upt and tw o sub-routine levels. program execution is triggered by sending a negative (bit 7 set) high address; execution starts at address xadr ($0083). the ram addresses betw een $0050 and $0082 are used b y the loader and are theref ore not available to the user during serial loading/executing. refer to figure c-7 shows a suitable circuit. figure c-9 shows address and data bus timing. c.4.4 ram parallel bootstrap load and execute the ram bootstr ap prog r am will star t loading the ram with e xter nal data (e .g. from a 2564 or 2764 epr om). bef ore loading a ne w b yte , the state of the pd4/an4 pin is chec k ed; if this pin goes to level 0, or if the ram is full, then control is given to the loaded program at address $0050. if the data is supplied b y a par allel interf ace , handshaking will be pro vided b y pc5 and pc6 according to figure c-10. if the data comes from an e xter nal epr om, the handshak e can be disabled by connecting together pc5 and pc6. figure c-8 sho ws a circuit that can be used to load the ram with shor t test prog rams . up to 8 progr ams can be loaded in tur n from the epr om. selection is accomplished b y means of the s witches connected to the epr om higher address lines (a8 through a10). if the user prog ram sets pc0 to le v el 1, the e xternal epr om will be disab led, render ing both por t a outputs and por t b inputs available. the eprom parallel bootstr ap loader circuit (figure c-6) can also be used, pro vided vpp is tied to v dd . the high order address lines will be at zero. the leds will stay off. table c-3 bootstrap vector targets in ram vector targets in ram sci interrupt $00e4 timer over?ow $00e7 timer output compare $00ea timer input capture $00ed irq $00f0 swi $00f3
mc68hc05b6 motorola c-15 mc68hc705b5 14 figure c-7 eprom (ram) serial bootstrap schematic diagram red programming error green programming ok 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k? 1.0f 100k? 1n914 reset run 0.01f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470? 470? red led green led + + vrh 22f 22f 22f 2 x 3k? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 10m? 4k7? 4k7? 12 k? bc239c bc309c 10k ? 1nf 1n5819 1 k? + serial boot erase check 47f + pd3 4 rdi tdo erase check red eprom not erased green eprom erased serial boot mc68hc705b5 3
motorola c-16 mc68hc05b6 mc68hc705b5 14 figure c-8 ram parallel bootstrap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd tcap2 tcmp2 tcmp1 plmb plma sclk tdo rdi vrh vrl pd7 pd6 pd5 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 nc osc1 osc2 tcap1 irq reset pd4 vpp6 vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe a8 a9 a10 a11 a12 ce vcc pgm vpp 20 2 25 24 23 14 22 10 9 8 7 6 5 4 1 26 27 28 21 12 13 15 16 17 18 19 11 3 +5v 3 x 4.7k? +5v +5v 16 x 100k? 1 2 p1 gnd +5v 100f 22pf 4.0 mhz 1n914 1k? 1.0f 22pf 10m? 100k? 1n914 reset run 0.01f u1 2764 +5v 18 x 100 k? + + nc mc68hc705b5
mc68hc05b6 motorola c-17 mc68hc705b5 14 c.4.5 bootstrap loader timing diagrams figure c-9 eprom parallel bootstrap loader timing diagram t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5 ms nominal) 1 machine cycle = 1/(2f 0 (xtal))
motorola c-18 mc68hc05b6 mc68hc705b5 14 figure c-10 ram parallel loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognised during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
mc68hc05b6 motorola c-19 mc68hc705b5 14 c.5 dc electrical characteristics note: the complete tab le of dc electr ical character istics can be f ound in section 11.3. the v alues contained in the f ollowing tab le should be used in conjunction with those quoted in that section. c.6 control timing note: the complete tab le of control timing can be f ound in section 11.5. the v alues contained in the f ollowing tab le should be used in conjunction with those quoted in that section. table c-4 additional dc electrical characteristics for mc68hc705b5 (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25?c) characteristic symbol min typ max unit input current port b and port c pull-down (v in = v ih ) i rpd 80 a eprom absolute maximum voltage v pp6 max v dd 18 v eprom programming voltage v pp6 15.0 15.5 16 v eprom programming current i pp6 18 ma eprom read voltage v pp6r v dd v dd v dd v table c-5 additional control timing for mc68hc705b5 (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25? c) characteristic symbol min typ max unit eprom programming time t prog 5 20 ms
motorola c-20 mc68hc05b6 mc68hc705b5 this page intentionally left blank 14
mc68hc05b6 motorola d-1 mc68hc05b16 14 d mc68hc05b16 the mc68hc05b16 is a device similar to the mc68hc05b6, but with increased ram, rom and self-chec k r om siz es . the entire mc68hc05b6 data sheet, including the electr ical characteristics, applies to the mc68hc05b16, with the exceptions outlined in this appendix. features ? 15 kbytes user rom ? 352 bytes of ram ? 496 bytes self-check rom ? 52-pin plcc, 56-pin sdip and 64-pin qfp packages d.1 self-check routines the self-chec k routines f or the mc68hc05b16 are identical to those of the mc68hc05b6 with the following exception. the count b yte on the mc68hc05b16 can be an y v alue up to 256 ($00). the ?rst 176 b ytes are loaded into ram i and the remainder is loaded into ram ii starting at $0250.
motorola d-2 mc68hc05b16 mc68hc05b16 14 figure d-1 mc68hc05b16 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 15120 bytes rom 352 bytes static ram 496 bytes self-check rom
mc68hc05b6 motorola d-3 mc68hc05b16 14 figure d-2 memory map of the mc68hc05b16 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $3ff0 stack ram 1 (176 bytes) $0250 $0200 $3e00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) user rom (15104 bytes) self-check rom (496 bytes) $0300 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b16 registers ram 11 (176 bytes) $3dff user vectors (14 bytes) $3ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $3ff4C5 $3ff6C7 $3ff8C9 $3ffaCb $3ffcCd $3ffeCf
motorola d-4 mc68hc05b16 mc68hc05b16 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. table d-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected
mc68hc05b6 motorola e-1 mc68hc705b16 14 e mc68hc705b16 the mc68hc705b16 is a de vice similar to the mc68hc05b6, b ut with increased ram and 15 kbytes of eprom instead of 6 kbytes of rom. in addition, the self-check routines available in the mc68hc05b6 are replaced b y bootstr ap ?r mware . the mc68hc705b16 is an o tprom (one-time programmable rom) v ersion of the mc68hc05b16, meaning that once the application progr am has been loaded in the epr om it can ne ver be er ased. the entire mc68hc05b6 data sheet applies to the mc68hc705b16, with the exceptions outlined in this appendix. features ? 15 kbytes eprom ? 352 bytes of ram ? 576 bytes bootstrap rom ? simultaneous programming of up to 8 bytes of eprom ? optional pull-down resistors available on all port b and port c pins ? 52-pin plcc and 64-pin qfp packages note: the electr ical char acter istics of the mc68hc05b6 as pro vided in section 11 do not apply to the mc68hc705b16. data speci?c to the mc68hc705b16 can be f ound in this appendix. t o ensure correct oper ation of the mc68hc705b16 after po w er-on, the de vice must be reset a second time after po w er-on. this can be done in softw are using the mc68hc705b16 watchdog. the following software sub-routine should be used: reset2 bset 0, $0c start watchdog stop stop causes immediate watchdog system reset the interrupt vector at $3ff0 and $3ff1 must be initialised with the reset2 address value.
motorola e-2 mc68hc705b16 mc68hc705b16 14 figure e-1 mc68hc705b16 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 15168 bytes eprom 352 bytes static ram 576 bytes vpp6 bootstrap rom
mc68hc05b6 motorola e-3 mc68hc705b16 14 figure e-2 memory map of the mc68hc705b16 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $3ff0 stack ram 1 (176 bytes) $0250 $0200 $3e00 $0050 port a data direction register port b data direction register port c data direction register e/eepr om/eclk control registe r a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user eprom (48 bytes) user eprom (15104 bytes) bootstrap rom 11 (496 bytes) $0300 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc705b16 registers ram 11 (176 bytes) $3dfe $3dff mask option register mask option register $3dfe bootstrap rom 1 (80 bytes) user vectors (14 bytes) $3ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $3ff4C5 $3ff6C7 $3ff8C9 $3ffaCb $3ffcCd $3ffeCf
motorola e-4 mc68hc705b16 mc68hc705b16 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. (4) this register is implemented in eprom; therefore reset has no effect on the individual bits. table e-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $3dfe rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola e-5 mc68hc705b16 14 e.1 eprom the mc68hc705b16 memory map is given in figure e-2. the device has a total of 15168 bytes of eprom (including 14 bytes for user vectors) and 256 bytes of eeprom. the epr om arr a y is supplied b y the vpp6 pin in both read and prog r am modes . t ypically the users software w ould be loaded into a prog r amming board where v pp6 is controlled b y one of the bootstr ap loader routines . it w ould then be placed in an application where no prog r amming occurs . in this case the vpp6 pin should be hardwired to v dd . warning: a minim um v dd v oltage m ust be applied to the vpp6 pin at all times , including power-on. failure to do so could result in permanent damage to the device. e.1.1 eprom read operation the e x ecution of a prog r am in the epr om address r ange or a load from the epr om are both read operations. the e6lat bit in the eprom/eeprom control register should be cleared to 0 which automatically resets the e6pgm bit. in this w a y the epr om is read lik e a nor mal r om. reading the eprom with the e6la t bit set will giv e data that does not correspond to the actual memory content. as interrupt vectors are in eprom, the y will not be loaded when e6la t is set. similarly, the bootstrap rom routines cannot be executed when e6la t is set. in read mode , the vpp6 pin must be at the v dd level. when entering the stop mode, the eprom is automatically set to the read mode. note: an erased byte reads as $00. e.1.2 eprom program operation typically the eprom will be programmed by the bootstrap routines resident in the on-chip rom. however , the user prog r am can be used to prog r am some epr om locations if the proper procedure is followed. in particular, the programming sequence must be r unning in ram, as the epr om will not be a vailab le f or code e x ecution while the e6la t bit is set. the v pp6 s witching must occur externally after the e6pgm bit is set, for example under control of a signal generated on a pin by the programming routine. note: when the part becomes a prom, only the cumulative progr amming of bits to logic 1 is possible if multiple programming is made on the same byte. to allow simultaneous progr amming of up to eight b ytes, these bytes m ust be in the same g roup of addresses which share the same most signi?cant address bits; only the three least signi?cant bits can change.
motorola e-6 mc68hc705b16 mc68hc705b16 14 e.1.3 eprom/eeprom/eclk control register e6lat eprom programming latch enable bit 1 (set) C address and up to eight data bytes can be latched into the eprom for further programming providing the e6pgm bit is cleared. 0 (clear) C data can be read from the epr om or ?r mw are r om; the e6pgm bit is reset to zero when e6lat is 0. stop, power-on and external reset clear the e6lat bit. note: after the t era1 erase time or t prog1 programming time, the e6la t bit has to be reset to zero in order to clear the e6pgm bit. e6pgm eprom program enable bit this bit is the epr om program enab le bit. it can be set to 1 to enab le progr amming only after e6la t is set and at least one b yte is wr itten to the epr om. it is not possib le to clear this bit using software but clearing e6lat will always clear e6pgm. note: the e6pgm bit can never be set while the e6lat bit is at zero. eclk see section 4.3. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 table e-2 eprom control bits description e6lat e6pgm description 0 0 read/execute in eprom 1 0 ready to write address/data to eprom 1 1 programming in progress
mc68hc05b6 motorola e-7 mc68hc705b16 14 e1era eeprom erase/programming bit pro viding the e1la t and e1pgm bits are at logic one , this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) C an erase operation will take place. 0 (clear) C a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. e1lat eeprom programming latch enable bit 1 (set) C address and data can be latched into the eeprom for further program or erase operations, providing the e1pgm bit is cleared. 0 (clear) C data can be read from the eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is 0. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1la t bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm eeprom charge pump enable/disable 1 (set) C internal charge pump generator switched on. 0 (clear) C internal charge pump generator switched off. when the charge pump gener ator is on, the resulting high v oltage is applied to the eepr om arr ay. this bit cannot be set bef ore the data is selected, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summar y of the eff ects of setting/clear ing bits 0, 1 and 2 of the control register are giv en in t ab le e-3. note: the e1pgm and e1era bits are cleared when the e1lat bit is at zero. table e-3 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
motorola e-8 mc68hc705b16 mc68hc705b16 14 e.1.4 mask option register rtim reset time this bit can modify the time t porl , where the reset pin is kept low after a power-on reset. 1 (set) C t porl = 16 cycles. 0 (clear) C t porl = 4064 cycles. rwat watchdog after reset this bit can modify the status of the w atchdog counter after reset. usually, the watchdog system is disab led after po w er-on or e xter nal reset b ut when this bit is set, it will be activ e immediately after the following resets (except in bootstrap mode). wwat watchdog during wait mode this bit can modify the status of the w atchdog counter in w ait mode . nor mally , the w atchdog system is disab led in w ait mode b ut when this bit is set, the w atchdog will be activ e in w ait mode. pbpd port b pull-down this bit, when programmed, connects a resistive pull-do wn on each pin of por t b. this pull-down, r pd , is active on a given pin only while it is an input. pcpd port c pull-down this bit, when prog r ammed, connects a resistiv e pull-do wn on each pin of por t c . this pull-do wn, r pd , is active on a given pin only while it is an input. (1) this register is implemented in eprom; therefore reset has no effect on the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) (1) $3dfe rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola e-9 mc68hc705b16 14 e.1.5 eeprom options register (optr) ee1p C eeprom protect bit in order to achie v e a higher deg ree of protection, the eepr om is eff ectiv ely split into tw o parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; par t 2 (224 b ytes from $0120 to $01ff) is protected b y the ee1p bit in the options register. 1 (set) C part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations. 0 (clear) C part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful. when this bit is set to 1 (er ased), the protection will remain until the ne xt po w er-on or e xternal reset. ee1p can only be written to 0 when the e1lat bit in the eeprom control register is set. note: the eeprom1 protect function is disabled while in bootstrap mode. sec secure bit this bit allows the eprom and eepr om1 to be secured from e xternal access . when this bit is in the erased state (set), the eprom and eeprom1 content is not secured and the device may be used in non user mode . when the sec bit is prog r ammed to z ero, the epr om and eepr om1 content is secured b y prohibiting entr y to the non user mode . to deactiv ate the secure bit, the epr om has to be er ased by e xposure to a high density ultr a violet light, and the de vice has to be entered into the epr om er ase v er i?cation mode with pd1 set. when the sec bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) C eeprom/eprom not protected. 0 (clear) C eeprom/eprom protected. (1) this register is implemented in eeprom; therefore reset has no effect on the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) $0100 ee1p sec not affected
motorola e-10 mc68hc705b16 mc68hc705b16 14 e.2 bootstrap mode the 432 b ytes of self-chec k ?r mw are on the mc68hc05b6 are replaced b y 576 b ytes of bootstr ap ?rmware. a detailed description of the modes of operation within bootstrap mode is given below. the bootstrap progr am in mask r om address locations $0200 to $024f and $3e00 to $3fef can be used to prog r am the epr om and the eepr om, to chec k if the epr om is er ased or to load and execute data in ram. after reset, while going to the bootstr ap mode , the v ector located at address $3fee and $3fef (reset) is f etched to star t e x ecution of the bootstr ap prog r am. t o place the par t in bootstr ap mode, the irq pin should be at + 9v with the tcap1 pin high dur ing tr ansition of the reset pin from low to high. the hold time on the irq and tcap1 pins is two clock cycles after the external reset pin is brought high. when the mc68hc705b16 is placed in the bootstr ap mode, the bootstrap reset vector is fetched and the bootstr ap ?r mw are star ts to e xecute . t ab le e-4 sho ws the conditions required to enter each level of bootstrap mode on the rising edge of reset. the bootstr ap prog r am ?rst copies par t of itself in ram (e xcept ram par allel load), as the program cannot be executed in rom during veri?cation/programming of the eprom. it then sets the tcmp1 output to a logic high level. table e-4 mode of operation selection irq pin tcap1 pin pd1 pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x x single chip + 9 volts v dd 0 0 x 0 erased eprom veri?cation (eev) + 9 volts v dd 1 0 0 0 erased eprom veri?cation; erase eeprom; eprom/eeprom parallel program/verify + 9 volts v dd 1 0 1 0 erased eprom veri?cation; erase eeprom; eprom/eeprom/ ram serial bootstrap load and execute + 9 volts v dd x x 0 1 ram parallel bootstrap load and execute (if sec bit = 1) + 9 volts v dd x x 1 1 serial eprom/eeprom/ram bootloader (if sec = 1) x = dont care
mc68hc05b6 motorola e-11 mc68hc705b16 14 figure e-3 modes of operation ?ow chart (1 of 2) pd3 set? eepr om1 er ased? tcap1 set? irq at 9v? pd2 set? pd4 set? reset program eprom; par allel load; g reen led ?ashes user mode green led on red led on non-user mode red led on green led on non-user mode a n y y y y n y n n n y n y bootstrap mode eprom not erased eprom veri?ed parallel e/eeprom bootstrap bad eprom programming n pd1 set? bulk erase eeprom1 red led on red led off n y y n b n y erased eprom veri?cation sec bit activ e? eprom er ased? prog r amming ok?
motorola e-12 mc68hc705b16 mc68hc705b16 14 figure e-4 modes of operation ?ow chart (2 of 2) negativ e address? pd4 set? pd3 set? transmit last four programmed locations a receive address receive four data execute ram program at $008b green led on load next ram byte ram 1 full? execute ram program at $0050 program e/eeprom data at address; green led ?ashes n y y y y n n serial e/eeprom (ram) bootstrap parallel bootstrap ram sec bit set? red led ?ashes b n y n
mc68hc05b6 motorola e-13 mc68hc705b16 14 e.2.1 erased eprom veri?cation if a non $00 b yte is detected, the red led is tur ned on and the routine stops (see figure e-3 and figure e-4). only when the entire epr om content is v er i?ed as er ased does the g reen led s witch on. pd1 is then chec k ed. if pd1=0, the bootstr ap progr am stops here and no prog ramming occurs until such time as a high le v el is sensed on pd1. if pd1=1, the bootstr ap prog r am proceeds to er ase the eepr om1 f or a nominal 100 ms (4.0 mhz cr ystal). it is then chec k ed f or complete er asure; if a non $ff b yte is detected, the red led is tur ned on, and er ase is perf or med a second time , and so on until total er asure is v er i?ed. at this point, both epr om and eepr om1 are completely er ased and the secur ity bit is cleared. the prog r amming oper ation can then be perfor med. a schematic diag r am of the circuit required f or erased eprom ver i?cation is sho wn in figure e-7. e.2.2 eprom/eeprom parallel bootstrap before the parallel bootstrap routines begin, the erased eprom veri?cation program is executed as descr ibed in section e.2.1. when pd2=0, the prog r amming time is set to 5 milliseconds with the bootstrap program and verify for the eprom taking approximately 15 seconds. the eprom is loaded in increasing address order with non epr om segments being skipped b y the loader . sim ultaneous prog r amming is perf or med b y reading eight b ytes of data bef ore actual programming is performed, thus the loading time of the internal eprom is divided by eight. par allel data is entered through p or t a, while the 14-bit address is output on por t b, pc0 to pc4 and tcmp2. if the data comes from an e xter nal epr om, the handshak e can be disab led b y connecting together pc5 and pc6. if the data is supplied b y a parallel interface, handshaking will be provided b y pc5 and pc6 according to the timing diag r am of figure e-5 (see also figure e-6). figure e-5 timing diagram with handshake data read data read address hdsk out (pc5) data hdsk in (pc6) f29
motorola e-14 mc68hc705b16 mc68hc705b16 14 during programming, the green led will ?ash at about 3 hz. upon completion of the programming operation, the contents of the eprom and eeprom1 are check ed against the e xter nal data source . if prog r amming is v er i?ed the g reen led sta ys on, while an error will cause the red led to be tur ned on. figure e-7 is a schematic diag r am of a circuit that can be used to program the eprom or to load and execute data in the ram. note: the entire epr om and eepr om1 can be loaded from the e xter nal source; if it is desired to leav e a segment undisturbed, the data f or this segment should be all z eros for eprom data and all $ffs for eeprom1 data. figure e-6 parallel eprom loader timing diagram t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5 ms nominal for eprom; 10ms for eeprom1)) 1 machine cycle = 1/(2f 0 (xtal))
mc68hc05b6 motorola e-15 mc68hc705b16 14 figure e-7 eprom parallel bootstrap schematic diagram vcc 28 1 vpp pgm 27 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe 14 22 10 9 8 7 6 5 4 26 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100f 22pf 4.0 mhz 1n914 1k? 1.0f 22pf 100k? 1n914 reset run 0.01f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k? nc tcmp1 tcmp2 plma plmb 470? 470? red led green led 4k7? 4k7? 12 k? bc239c bc309c 10k ? 27c128 + + vrh red led programming failed green led programming ok 25 1nf 1n5819 1 k? + ram eprom green led eprom erased 47f + erase check & boot eprom erase check vpp1 red led eprom not erased boot erase check a13 20 mc68hc705b16 mcu
motorola e-16 mc68hc705b16 mc68hc705b16 14 e.2.3 eeprom/eprom/ram serial bootstrap f or er ased epr om v er i?cation, pd4 m ust be at 0. in this case , er ased epr om v eri?cation executes as described in section e.2.1 before control is given to the serial routine. if pd4 is at 1, the program initially checks the state of the security bit. if the security bit is active (0), the prog r am will not enter ser ial bootstr ap and the red led will ?ash. otherwise the ser ial bootstrap program will be executed according to figure e-3 and figure e-4. the serial routine communicates through the sci with an external host, typically a pc, by means of an rs232 link at 9600 baud, 8-bit, no par ity and full duple x. ref er to figure e-8 f or a schematic diagram of a suitable circuit. note: data for mat is not ascii, b ut 8-bit binar y , so a complementar y program m ust be r un by the host to supply the required f or mat. such a prog r am is a vailable f or the ibm pc from motorola. the eprom bootstr ap routines are used to customise the o tp eprom. t o increase the speed of prog r amming the 15 kb ytes , f our b ytes are prog r ammed while the data is sim ultaneously transmitted back and forw ard in full duple x. this implies that while 4 b ytes are being prog rammed the next 4 bytes are received and the preceding 4 bytes are echoed. the format accepted by the serial loader is as follows: 1 eprom locations [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] address n must have the tw o least signi?cant bits at z ero so that n, n+1, n+2 and n+3 have identical most signi?cant bits. these blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new group. 2 eeprom1 locations [address n high] [address n lo w] [data(n)] [dumm y data 1] [dumm y data 2] [dumm y data 3] the same four byte protocol of data exchange is used, but only the ?rst data value is progr ammed at address n. the three f ollowing dumm y data v alues m ust be sent to be in agreement with the protocol, but are not signi?cant. the protocol is as follows: 1 the mc68hc705b16 sends the last two bytes programmed to the host as a prompt; this also allows the host to verify that programming has been carried out correctly. 2 in response to the ?rst byte prompt, the host sends the ?rst address byte. 3 after receiving the ?rst address byte, the mc68hc705b16 sends the next byte programmed.
mc68hc05b6 motorola e-17 mc68hc705b16 14 figure e-8 ram/eprom/eeprom serial bootstrap schematic diagram green led programming ended flashing green led programming 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k? 1.0f 100k? 1n914 reset run 0.01f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470? 470? red led green led + + vrh 22f 22f 22f 2 x 3k? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 4k7? 4k7? 12 k? bc239c bc309c 10k ? 1nf 1n5819 1 k? + serial boot erase check 47f + pd3 rdi tdo erase check red led eprom not erased green led eprom erased serial boot & serial boot erase check and serial boot eprom erase check vpp1 3 u2 mc68hc705b16 mcu (socket)
motorola e-18 mc68hc705b16 mc68hc705b16 14 4 the e xchange of data contin ues until the mc68hc705b16 has sent the f our data b ytes and the host has sent the 2 address data b ytes and 4 data b ytes. 5 if the data is different from $00 for eprom or $ff for eeprom, it is progr ammed at the address pro vided, while the ne xt address and b ytes are received and the previous data is echoed. 6 loop to 1. after reset, the mc68hc705b16 serial bootstrap routine will ?rst echo two blocks of four bytes at $00, as no data is programmed yet. if the data receiv ed is $00 f or epr om locations or $ff f or eeprom locations, no programming in the epr om and eepr om1 tak es place , and the contents of the accessed location are retur ned as a prompt. the entire eprom/eeprom memory can be read in this fashion (serial dump). w arning: when using this function with a prog r ammed de vice , the de vice m ust be placed into ram/epr om/eepr om ser ial bootstr ap mode without epr om er ase chec k (pd4 = 1). serial ram loading and execute can be accomplished in this mode. a ram byte will be written if the address sent by the host in the serial protocol points to the ram. ram b ytes $008bC$00e3 and $0250C$02ed are a vailab le f or user test prog rams . a 10-b yte stac k resides at the top of ram i, allowing, for example , one interr upt and tw o sub-routine le vels. the ram addresses betw een $0050 and $008a are used b y the loader and are theref ore not a vailable to the user during serial loading/executing. if the sec bit is at 1, prog r am e x ecution is tr iggered b y sending a negativ e (bit 7 set) high address; execution starts at address xadr ($008b). in the ram bootloader mode , all interr upt v ectors are mapped to pseudo-v ectors in ram (see tab le e-5). this allo ws prog r ammers to use their o wn ser vice-routine addresses . each pseudo-v ector is allo w ed three b ytes of space r ather than the tw o b ytes f or nor mal v ectors, because an e xplicit jump (jmp) opcode is needed to cause the desired jump to the user s service routine address. table e-5 bootstrap vector targets in ram vector targets in ram sci interrupt $02ee timer over?ow $02f1 timer output compare $02f4 timer input capture $02f7 irq $02fa swi $02fd
mc68hc05b6 motorola e-19 mc68hc705b16 14 e.2.4 ram parallel bootstrap the program ?rst chec ks the state of the secur ity bit. if the sec bit is activ e, i.e. 0, the program will not enter the ram bootstr ap mode and the red led will ?ash. otherwise the ram bootstr ap program will start loading the ram with external data (e .g. from a 2564 or 2764 epr om). before loading a ne w b yte the state of the pd4/an4 pin is chec k ed. if this pin goes to le v el 0, or if the ram is full, then control is giv en to the loaded prog r am at address $0050. see figure e-3 and figure e-4. if the data is supplied b y a par allel interf ace , handshaking will be pro vided b y pc5 and pc6 according to figure e-9. if the data comes from an e xter nal epr om, the handshak e can be disabled by connecting together pc5 and pc6. figure e-10 pro vides a schematic diag r am of a circuit that can be used to load the ram with shor t test prog rams . up to 8 prog r ams can be loaded in tur n from the epr om. selection is accomplished b y means of the s witches connected to the epr om higher address lines (a8 through a10). if the user prog r am sets pc0 to le v el 1, this will disab le the external eprom, thus render ing both por t a output and por t b input a vailable . the epr om par allel bootstr ap loader schematic can also be used (figure e-7), pro vided vpp is at v dd lev el. the high order address lines will be at zero. the leds will stay off. figure e-9 parallel ram loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognised during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
motorola e-20 mc68hc705b16 mc68hc705b16 14 e.2.4.1 jump to start of ram ($0050) pd4 m ust be high dur ing the ?rst 49 prog r am cycles and pulled lo w bef ore the 68th cycle f or immediate jump execution at address $0050. note: figure e-10 ram parallel bootstrap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd tcap2 tcmp2 tcmp1 plmb plma sclk tdo rdi vrh vrl pd7 pd6 pd5 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 nc osc1 osc2 tcap1 irq reset pd4 vpp6 vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe a8 a9 a10 a11 a12 ce vcc pgm vpp 20 2 25 24 23 14 22 10 9 8 7 6 5 4 1 26 27 28 21 12 13 15 16 17 18 19 11 3 +5v 3 x 4.7k? +5v 16 x 100k? 1 2 p1 gnd +5v 100f 22pf 4.0 mhz 1n914 1k? 1.0f 22pf 100k? 1n914 reset run 0.01f u1 2764 +5v 18 x 100 k? + + nc vpp1 u2 mc68hc705b16 mcu (socket)
mc68hc05b6 motorola e-21 mc68hc705b16 14 e.2.5 maximum ratings note: this de vice contains circuitr y designed to protect against damage due to high electrostatic v oltages or electr ic ?elds . ho wever , it is recommended that nor mal precautions be tak en to a v oid the application of an y v oltages higher than those giv en in the maximum ratings tab le to this high impedance circuit. f or maximum reliability all unused inputs should be tied to either v ss or v dd . (1) all voltages are with respect to v ss . (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. table e-6 maximum ratings rating symbol value unit supply voltage (1) v dd C 0.5 to +7.0 v input voltage v in v ss C 0.5 to v dd + 0.5 v input voltage C self-check mode ( irq pin only) v in v ss C 0.5 to 2v dd + 0.5 v operating temperature range C standard (mc68hc705b16) C extended (mc68hc705b16c) C industrial (mc68hc705b16v) C automotive (mc68hc705b16m) t a t l to t h 0 to +70 C40 to +85 C40 to +105 C40 to +125 ?c storage temperature range t stg C 65 to +150 ?c current dr ain per pin (e xcluding vdd and vss) (2) C source C sink i d i s 25 45 ma ma
motorola e-22 mc68hc705b16 mc68hc705b16 14 e.2.6 thermal characteristics and power considerations the average chip junction temperature, t j , in degrees celsius can be obtained from the following equation: [1] where: t a = ambient temperature (?c) q ja = package thermal resistance, junction-to-ambient (?c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ? v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [2] solving equations [1] and [2] for k gives: [3] where k is a constant f or a particular par t. k can be deter mined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table e-7. table e-7 package thermal characteristics characteristics symbol value unit thermal resistance C 64-pin quad ?at package q ja 50 ?c/w C plastic 56 pin shrink dil package not available for this device C plastic 52 pin plcc package q ja 50 ?c/w figure e-11 equivalent test load t j t a p d q ja ( ) + = p d k t j 273 + --------------------- = k p d t a 273 + ( ) q ja p d 2 + = v dd = 4.5/3.0 v r2 r1 c test point voltage pins r1 r2 c 4.5v pa0C7, pb0C7, pc0C7 3.26 k? 2.38 k? 50pf 3.0v pa0C7, pb0C7, pc0C7 10.91 k? 6.32 k? 50pf
mc68hc05b6 motorola e-23 mc68hc705b16 14 e.2.7 dc electrical characteristics table e-8 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.8 v dd C 0.8 v dd C 0.4 v dd C 0.4 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.1 0.4 0.4 1 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd 5.0 1.0 1.5 0.9 2 6 1.5 2 1 10 20 60 60 ma ma ma ma a a a a eprom absolute maximum voltage programming voltage programming current read voltage v pp6 max v pp6 i pp6 v pp6r v dd 15 v dd 15.5 50 v dd 18 16 64 v dd 10% v v ma v high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current port b and port c pull-down (v in = v ih ) i rpd 80 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 5 a capacitance por ts (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c in c in c in 12 22 12 8 pf pf pf pf
motorola e-24 mc68hc705b16 mc68hc705b16 14 (1) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an e xternal square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all por ts con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance.
mc68hc05b6 motorola e-25 mc68hc705b16 14 (1) all i dd measurements taken with suitab le decoupling capacitors across the po w er supply to suppress the tr ansient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. table e-9 dc electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.3 v dd C 0.3 v dd C 0.1 v dd C 0.1 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.1 0.2 0.4 0.6 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd 2.0 0.8 1.0 0.4 1 3 1 1.5 0.5 10 10 40 40 ma ma ma ma a a a a high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current port b and port c pull-down (v in = v ih ) i rpd 80 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 5 a capacitance por ts (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c in c in c in 12 22 12 8 pf pf pf pf
motorola e-26 mc68hc705b16 mc68hc705b16 14 e.2.8 a/d converter characteristics e.3 control timing (1) performance veri?ed down to 2.5v ?vr, b ut accuracy is tested and guaranteed at ?vr = 5v10%. (2) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table e-10 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 1 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r (1) minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (3) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
mc68hc05b6 motorola e-27 mc68hc705b16 14 (1) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table e-11 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 1 lsb quantization error uncertainty due to converter resolution 1 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 2 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion internal rc oscillator 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling internal rc oscillator (1) 12 s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (2) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
motorola e-28 mc68hc705b16 mc68hc705b16 14 (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table e-12 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc dc 2.1 2.1 mhz mhz cycle time (see figure 9-1) t cyc 480 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 100 ms a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eprom programming time t prog 5 20 ms eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t era t era t era t era 10 10 10 10 ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t prog t prog t prog t prog 10 10 15 20 ms ms ms ms timer (see figure e-12) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 125 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 90 ns
mc68hc05b6 motorola e-29 mc68hc705b16 14 (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table e-13 control timing for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 1.0 1.0 mhz mhz cycle time (see figure 9-1) t cyc 1000 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 100 ms a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eprom programming time t prog 5 20 ms eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t era t era t era t era 30 30 30 30 ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 85 (industrial) C 40 to 125 (automotive) t prog t prog t prog t prog 30 30 30 30 ms ms ms ms timer (see figure e-12) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 250 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 200 ns
motorola e-30 mc68hc705b16 mc68hc705b16 14 figure e-12 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
mc68hc05b6 motorola f-1 mc68hc05b32 14 f mc68hc05b32 the mc68hc05b32 is a de vice similar to the mc68hc05b6, b ut with increased ram and r om sizes . the entire mc68hc05b6 data sheet applies to the mc68hc05b32, with the e xceptions outlined in this appendix. features ? 31248 bytes user rom ? no page zero rom ? 528 bytes of ram ? 638 bytes of self-check rom ? 52-pin plcc, 56-pin sdip and 64-pin qfp packages note: preliminary electr ical speci?cations f or the mc68hc05b32 should be tak en as being identical to those f or the mc68hc705b32. when silicon is fully a vailable, the part will be re-characterised and new data made available.
motorola f-2 mc68hc05b6 mc68hc05b32 14 figure f-1 mc68hc05b32 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 32 kbytes rom 528 bytes static ram 638 bytes vpp6 self-check rom
mc68hc05b6 motorola f-3 mc68hc05b32 14 figure f-2 memory map of the mc68hc05b32 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $7fdf $7ff0 stack ram i (176 bytes) $0250 $0200 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f user rom (31232 bytes) self-check rom iii (478 bytes) $03b0 $7fe0 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b32 registers ram ii (352 bytes) $0400 mask option register mask option register $7fde self-check rom i (80 bytes) self-check rom vectors (16 bytes) self-check rom ii (80 bytes) $7e00 $7fde user vectors (14 bytes) $7ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $7ff4C5 $7ff6C7 $7ff8C9 $7ffaCb $7ffcCd $7ffeCf
motorola f-4 mc68hc05b6 mc68hc05b32 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. (4) this register is implemented in rom; therefore reset has no effect on the individual bits. table f-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $7fde rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola g-1 mc68hc705b32 14 g mc68hc705b32 the mc68hc705b32 is an epr om v ersion of the mc68hc05b32, with the r om replaced by a similar amount of epr om and with a bootstr ap mode instead of a self-chec k mode . the entire mc68hc05b6 data sheet applies to the mc68hc705b32, with the e xceptions outlined in this appendix. features ? 31248 bytes user eprom ? no page zero eprom at $20C$4f ? 528 bytes of ram ? 638 bytes bootstrap rom instead of 432 bytes of self-check rom ? simultaneous programming of up to 16 bytes of eprom ? 52-pin plcc, 56-pin sdip and 64-pin qfp packages note: the electrical character istics from the mc68hc05b6 data sheet should not be used f or the mc68hc705b32. data speci?c to this de vice can be f ound in section g.2.6 and section g.2.8.
motorola g-2 mc68hc05b6 mc68hc705b32 14 figure g-1 mc68hc705b32 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 32 kbytes eprom 528 bytes static ram 638 bytes vpp6 bootstrap rom
mc68hc05b6 motorola g-3 mc68hc705b32 14 figure g-2 memory map of the mc68hc705b32 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $7fde $7ff0 stack ram 1 (176 bytes) $0250 $0200 $0050 port a data direction register port b data direction register port c data direction register e/eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f bootstrap rom ii (80 bytes) bootstrap rom vectors (16 bytes) $03b0 $7fe0 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc705b32 registers ram 11 (352 bytes) $0400 mask option register mask option register $7fde bootstrap rom i (80 bytes) user eprom (31232 bytes) bootstrap rom iii (478 bytes) $7e00 user vectors (14 bytes) $7ff2C3 sci timer over?ow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $7fdf $7ff4C5 $7ff6C7 $7ff8C9 $7ffaCb $7ffcCd $7ffeCf
motorola g-4 mc68hc05b6 mc68hc705b32 14 (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; therefore reset has no effect on the individual bits. (4) this register is implemented in eprom; therefore reset has no effect on the individual bits. table g-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 unde?ned port b data (portb) $0001 unde?ned port c data (portc) $0002 pc2/ eclk unde?ned port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 unde?ned port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eeprom/eclk control $0007 0 e6lat e6pgm eclk e1era e1lat e1pgm u000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl unde?ned sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 unde?ned input capture high 1 $0014 unde?ned input capture low 1 $0015 unde?ned output compare high 1 $0016 unde?ned output compare low 1 $0017 unde?ned timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c unde?ned input capture low 2 $001d unde?ned output compare high 2 $001e unde?ned output compare low 2 $001f unde?ned options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $7fde rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola g-5 mc68hc705b32 14 g.1 eprom figure g-2 sho ws the mc68hc705b32 memor y map . the de vice has a total of 31232 b ytes of eprom (including 14 bytes for user vectors) and 256 bytes of eeprom. the epr om arr a y is supplied b y the vpp6 pin in both read and prog r am modes . t ypically the users softw are will be loaded into a prog r amming board where v pp6 is controlled b y one of the bootstrap loader routines . it will then be placed in an application where no prog ramming occurs. in this case the vpp6 pin should be hardwired to v dd . warning: a minim um v dd v oltage m ust be applied to the vpp6 pin at all times , including power-on. failure to do so could result in permanent damage to the device. g.1.1 eprom read operation the e x ecution of a prog r am in the epr om address r ange or a load from the epr om are both read operations. the e6lat bit in the eprom/eeprom control register should be cleared to 0 which automatically resets the e6pgm bit. in this w a y the epr om is read lik e a nor mal r om. reading the eprom with the e6la t bit set will giv e data that does not correspond to the actual memory content. as interrupt vectors are in eprom, the y will not be loaded when e6la t is set. similarly, the bootstrap rom routines cannot be executed when e6la t is set. in read mode , the vpp6 pin must be at the v dd level. when entering the stop mode, the eprom is automatically set to the read mode. note: an erased byte reads as $00. g.1.2 eprom program operation typically, the eprom will be programmed by the bootstr ap routines resident in the on-chip r om. however , the user prog r am can be used to prog r am some epr om locations if the proper procedure is followed. in particular, the programming sequence must be r unning in ram, as the epr om will not be a vailab le f or code e x ecution while the e6la t bit is set. the v pp6 s witching must occur exter nally after epgm is set, f or e xample under control of a signal gener ated on a pin by the programming routine. note: when the part becomes a prom, only the cumulative progr amming of bits to logic 1 is possible if multiple programming is made on the same byte. to allow simultaneous progr amming of up to sixteen b ytes , these b ytes m ust be in the same g roup of addresses which share the same most signi?cant address bits; only the f our lsbs can change .
motorola g-6 mc68hc05b6 mc68hc705b32 14 g.1.3 eprom/eeprom control register e6lat eprom programming latch enable bit 1 (set) C address and up to sixteen data b ytes can be latched into the epr om for further programming providing the e6pgm bit is cleared. 0 (clear) C data can be read from the epr om or ?r mw are r om; the e6pgm bit is reset to zero when e6lat is 0. stop, power-on and external reset clear the e6lat bit. note: after the t era1 erase time or t prog1 programming time, the e6la t bit has to be reset to zero in order to clear the e6pgm bit. e6pgm eprom program enable bit this bit is the epr om program enab le bit. it can be set to 1 to enab le progr amming only after e6la t is set and at least one b yte is wr itten to the epr om. it is not possib le to clear this bit using software but clearing e6lat will always clear e6pgm. note: all combinations are not sho wn in the abo v e tab le , since the e6pgm bit is cleared when the e6lat bit is at zero, and will result in a read condition. eclk see section 4.3. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eeprom/eclk control $0007 0 e6lat e6pgm eclk e1era e1lat e1pgm u000 0000 table g-2 eprom control bits description e6lat e6pgm description 0 0 read/execute in eprom 1 0 ready to write address/data to eprom 1 1 programming in progress
mc68hc05b6 motorola g-7 mc68hc705b32 14 e1era eeprom erase/programming bit pro viding the e1la t and e1pgm bits are at logic one , this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) C an erase operation will take place. 0 (clear) C a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. e1lat eeprom programming latch enable bit 1 (set) C address and data can be latched into the eeprom for further program or erase operations, providing the e1pgm bit is cleared. 0 (clear) C data can be read from the eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is 0. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1la t bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm eeprom charge pump enable/disable 1 (set) C internal charge pump generator switched on. 0 (clear) C internal charge pump generator switched off. when the charge pump gener ator is on, the resulting high v oltage is applied to the eepr om arr ay. this bit cannot be set bef ore the data is selected, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summar y of the eff ects of setting/clear ing bits 0, 1 and 2 of the control register are giv en in t ab le g-3. note: the e1pgm and e1era bits are cleared when the e1lat bit is at zero. table g-3 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
motorola g-8 mc68hc05b6 mc68hc705b32 14 g.1.4 mask option register rtim this bit can modify the time t porl , where the reset pin is kept low after a power-on reset. 1 (set) C t porl = 16 cycles. 0 (clear) C t porl = 4064 cycles. rwat this bit can modify the status of the w atchdog counter after reset. usually, the watchdog system is disab led after po w er-on or e xter nal reset b ut when this bit is set, it will be activ e immediately after the following resets (except in bootstrap mode). wwat this bit can modify the status of the w atchdog counter in w ait mode . nor mally , the w atchdog system is disab led in w ait mode b ut when this bit is set, the w atchdog will be activ e in w ait mode. pbpd this bit, when prog r ammed, connects a resistiv e pull-do wn on all 8 pins of por t b. this pull-down, r pd , is active on a given pin only while it is an input. pcpd this bit, when prog r ammed, connects a resistiv e pull-do wn on all 8 pins of por t c . this pull-do wn, r pd , is active on a given pin only while it is an input. (1) because this register is implemented in eprom, reset has no effect on the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) (1) $7fde rtim rwat wwat pbpd pcpd not affected
mc68hc05b6 motorola g-9 mc68hc705b32 14 g.1.5 options register (optr) ee1p C eeprom protect bit in order to achie v e a higher deg ree of protection, the eepr om is eff ectiv ely split into tw o parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; par t 2 (224 b ytes from $0120 to $01ff) is protected b y the ee1p bit of the options register. 1 (set) C part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations. 0 (clear) C part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful. when this bit is set to 1 (er ased), the protection will remain until the ne xt po w er-on or e xternal reset. ee1p can only be written to 0 when the e1lat bit in the eeprom control register is set. note: the eeprom1 protect function is disabled while in bootstrap mode. sec secure bit this bit allows the eprom and eepr om1 to be secured from e xternal access . when this bit is in the erased state (set), the eprom and eeprom1 content is not secured and the device may be used in non user mode . when the sec bit is prog r ammed to z ero, the epr om and eepr om1 content is secured b y prohibiting entr y to the non user mode . to deactiv ate the secure bit, the epr om has to be er ased by e xposure to a high density ultr a violet light, and the de vice has to be entered into the epr om er ase v er i?cation mode with pd1 set. when the sec bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) C eeprom/eprom not protected. 0 (clear) C eeprom/eprom protected. (1) because this register is implemented in eeprom, reset has no effect on the individual bits. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) $0100 ee1p sec not affected
motorola g-10 mc68hc05b6 mc68hc705b32 14 g.2 bootstrap mode the 432 b ytes of self-chec k ?r mw are on the mc68hc05b6 are replaced b y 654 b ytes of bootstr ap ?rmware. a detailed description of the modes of operation within bootstrap mode is given below. the bootstrap program in mask r om address locations $0200 to $024f , $03b0 to $3fff, $7e00 to $7fdd and $7fe0 to $7fef can be used to prog ram the eprom and the eeprom, to check if the eprom is erased or to load and execute data in ram. after reset, while going to the bootstr ap mode , the v ector located at address $7fee and $7fef ( reset ) is f etched to star t e x ecution of the bootstr ap prog r am. t o place the par t in bootstr ap mode, the irq pin should be at 2xv dd with the tcap1 pin high dur ing transition of the reset pin from lo w to high. the hold time on the irq and tcap1 pins is tw o cloc k cycles after the external reset pin is brought high. when the mc68hc705b32 is placed in the bootstr ap mode , the bootstr ap reset v ector will be fetched and the bootstrap ?rmware will start to execute. table g-4 shows the conditions required to enter each level of bootstrap mode on the rising edge of reset. the bootstr ap prog r am will ?rst cop y par t of itself in ram (e xcept ram par allel load), as the progr am cannot be e xecuted in rom during veri?cation/progr amming of the epr om. it will then set the tcmp1 output to a logic high le v el, unlik e the mc68hc05b6 which k eeps tcmp1 lo w . this can be used to distinguish betw een the tw o circuits and, in par ticular, f or selection of the vpp le vel and current capability. table g-4 mode of operation selection irq pin tcap1 pin pd1 pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x x single chip + 9 volts v dd 0 0 0 x erased eprom veri?cation + 9 volts v dd 1 0 0 0 erased eprom veri?cation; erase eeprom; eprom/eeprom parallel program/verify + 9 volts v dd 0 1 0 0 erased eprom veri?cation; no eeprom erase if sec is zero (parallel mode) + 9 volts v dd 1 1 0 0 erased eprom veri?cation; erase eeprom; eprom parallel program/verify (no e 2 ) + 9 volts v dd x 1 1 0 jump to start of ram ($0051); sec bit = 0 + 9 volts v dd 0 1 0 1 eprom and eeprom veri?cation; sec bit = 0 (parallel mode) + 9 volts v dd x x 1 1 ser ial ram load/e x ecute C similar to mc68hc05b6 b ut can ?ll ram i, ii and iii x = dont care
mc68hc05b6 motorola g-11 mc68hc705b32 14 figure g-3 modes of operation ?ow chart (1 of 2) red led on tcap1 set? sec bit activ e? pd3 set? reset user mode red led on non-user mode non-user mode n y y y y n y n n bootstrap mode parallel e/eeprom bootstrap n pd4 set? y erased eprom veri?cation serial ram load/execute n pd2 set? y n jump to ram ($0051) pd2 set? n pd1 set? y n sec bit activ e? red led on y n pd4 set? y epr om er ased? n y y green led on pd1 set? n erase eeprom1 red led off n a b c sec bit activ e? irq at 2xv dd ?
motorola g-12 mc68hc05b6 mc68hc705b32 14 figure g-4 modes of operation ?ow chart (2 of 2) data v er i?ed? y pd2 set? n n red led on a base address = $400 (eprom only) base address = $100 (epr om and eepr om) y n green led on b c pd2 set? n y base address = $400 (eprom only) base address = $400 (eprom only)
mc68hc05b6 motorola g-13 mc68hc705b32 14 g.2.1 erased eprom veri?cation if a non $00 b yte is detected, the red led will be tur ned on and the routine will stop (see figure g-3 and figure g-4). only when the whole epr om content is v er i?ed as er ased will the g reen led be tur ned on. pd1 is then chec k ed. if pd1=0, the bootstr ap prog r am stops here and no progr amming occurs until such time as a high le v el is sensed on pd1. if pd1 = 1, the bootstr ap program proceeds to erase the eeprom1 f or a nominal 2.5 seconds (4.0 mhz cr ystal). it is then check ed f or complete er asure; if an y eepr om b yte is not er ased, the prog r am will stop bef ore er asing the sec b yte . when both epr om and eepr om1 are completely er ased and the secur ity bit is cleared the prog r amming oper ation can be perf or med. a schematic diag r am of the circuit required for erased eprom veri?cation is shown in figure g-7. g.2.2 eprom/eeprom parallel bootstrap within this mode there are various subsections which can be utilised by correctly con?guring the port pins shown in table g-4. the er ased epr om v er i?cation prog r am will be e x ecuted ?rst as descr ibed in section g.2.1. when pd2=0, the prog r amming time is set to 5 milliseconds with the bootstr ap progr am and v erify f or the epr om taking appro ximately 15 seconds . the epr om will be loaded in increasing address order with non epr om segments being skipped b y the loader . sim ultaneous progr amming is perf or med b y reading sixteen b ytes of data bef ore actual prog r amming is perfor med, thus dividing the loading time of the inter nal eprom b y 16. if an y bloc k of 16 epr om b ytes or 1 eepr om b yte of data is in the er ased state , no prog r amming tak es place , thus speeding up the execution time. par allel data is entered through p or t a, while the 15-bit address is output on por t b, pc0 to pc4 and tcmp1 and tcmp2. if the data comes from an e xter nal epr om, the handshak e can be disab led b y connecting together pc5 and pc6. if the data is supplied b y a par allel interf ace, handshake will be provided b y pc5 and pc6 according to the timing diag ram of figure g-5 (see also figure g-6). during programming, the green led will ?ash at about 3 hz. upon completion of the prog r amming oper ation, the epr om and eepr om1 content will be check ed against the e xter nal data source . if prog r amming is v er i?ed the g reen led will sta y on, while an error will cause the red led to be tur ned on. figure g-7 is a schematic diag r am of a circuit which can be used to program the eprom or to load and execute data in the ram. note: the entire epr om and eepr om1 can be loaded from the e xter nal source; if it is desired to lea v e a segment undisturbed, the data f or this segment should be all $00s for eprom data and all $ffs for eeprom1 data.
motorola g-14 mc68hc05b6 mc68hc705b32 14 figure g-5 timing diagram with handshake figure g-6 parallel eprom loader timing diagram data read data read address hdsk out (pc5) data hdsk in (pc6) f29 t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5 ms nominal for eprom; 10ms for eeprom1)) 1 machine cycle = 1/(2f 0 (xtal))
mc68hc05b6 motorola g-15 mc68hc705b32 14 figure g-7 eprom parallel bootstrap schematic diagram vcc 28 1 vpp pgm 27 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe 14 22 10 9 8 7 6 5 4 26 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100f 22pf 4.0 mhz 1n914 1k? 1.0f 22pf 100k? 1n914 reset run 0.01f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k? nc tcmp1 tcmp2 plma plmb 470? 470? red led green led 4k7? 4k7? 12 k? bc239c bc309c 10k ? 27c256 + + vrh red led programming failed green led programming ok 25 1nf 1n5819 1 k? + ram eprom green led eprom erased 47f + erase check & boot eprom erase check vpp1 red led eprom not erased boot erase check a13 20 mc68hc705b32 mcu a14 verify program eprom eprom
motorola g-16 mc68hc05b6 mc68hc705b32 14 g.2.3 serial ram loader this mode is similar to the ram load/e xecute program f or the mc68hc05b6 descr ibed in section 2.2, with the additional f eatures listed belo w . t ab le g-4 sho ws the entr y conditions required f or this mode. if the ?rst b yte is less than $b0, the bootloader beha ves e xactly as the mc68hc05b6, i.e . count byte followed by data stored in $0050 to $00ff. if the count byte is larger than ram i (176 bytes) then the code continues to ?ll ram ii then ram iii. in this case the count byte is ignored and the program ex ecution begins at $0051 once the total ram area is ?lled or if no data is receiv ed for 5 milliseconds. the user must take care when using branches or jumps as his code will be relocated in ram i, ii and iii. if the user intends to use the stac k in his prog r am, he should send nop s to ?ll the desired stack area. in the ram bootloader mode , all interr upt v ectors are mapped to pseudo-v ectors in ram (see tab le g-5). this allo ws prog r ammers to use their o wn ser vice-routine addresses . each pseudo-v ector is allo w ed three b ytes of space r ather than the tw o b ytes f or nor mal v ectors, because an e xplicit jump (jmp) opcode is needed to cause the desired jump to the users service-routine address. g.2.3.1 jump to start of ram ($0051) the jump to start of ram program will be executed when bring the de vice out of reset with pd2 and pd3 at 1 and pd4 at 0. table g-5 bootstrap vector targets in ram vector targets in ram sci interrupt $0063 timer over?ow $0060 timer output compare $005d timer input capture $005a irq $0057 swi $0054
mc68hc05b6 motorola g-17 mc68hc705b32 14 figure g-8 ram load and execute schematic diagram green led programming ended flashing green led programming 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k? 1.0f 100k? 1n914 reset run 0.01f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470? 470? red led green led + + vrh 22f 22f 22f 2 x 3k? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 4k7? 4k7? 12 k? bc239c bc309c 10k ? 1nf 1n5819 1 k? + serial boot erase check 47f + pd3 rdi tdo erase check red led eprom not erased green led eprom erased serial boot & serial boot erase check and serial boot eprom erase check vpp1 3 u2 mc68hc705b32 mcu (socket)
motorola g-18 mc68hc05b6 mc68hc705b32 14 figure g-9 parallel ram loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognised during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
mc68hc05b6 motorola g-19 mc68hc705b32 14 g.2.4 maximum ratings note: this de vice contains circuitr y designed to protect against damage due to high electrostatic v oltages or electr ic ?elds . ho wever , it is recommended that nor mal precautions be tak en to a v oid the application of an y v oltages higher than those giv en in the maximum ratings tab le to this high impedance circuit. f or maximum reliability all unused inputs should be tied to either v ss or v dd . (1) all voltages are with respect to v ss . (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. table g-6 maximum ratings rating symbol value unit supply voltage (1) v dd C 0.5 to +7.0 v input voltage v in v ss C 0.5 to v dd + 0.5 v input voltage C self-check mode ( irq pin only) v in v ss C 0.5 to 2v dd + 0.5 v operating temperature range C standard (mc68hc705b32) C extended (mc68hc705b32c) C industrial (mc68hc705b32v) C automotive (mc68hc705b32m) t a t l to t h 0 to +70 C40 to +85 C40 to +105 C40 to +125 ?c storage temperature range t stg C 65 to +150 ?c current dr ain per pin (e xcluding vdd and vss) (2) C source C sink i d i s 25 45 ma ma
motorola g-20 mc68hc05b6 mc68hc705b32 14 g.2.5 thermal characteristics and power considerations the average chip junction temperature, t j , in degrees celsius can be obtained from the following equation: [4] where: t a = ambient temperature (?c) q ja = package thermal resistance, junction-to-ambient (?c/w) p d = p int + p i/o (w) p int = internal chip power = i dd ? v dd (w) p i/o = power dissipation on input and output pins (user determined) an approximate relationship between p d and t j (if p i/o is neglected) is: [5] solving equations [1] and [2] for k gives: [6] where k is a constant f or a particular par t. k can be deter mined by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained for any value of t a by solving the above equations. the package thermal characteristics are shown in table g-7. table g-7 package thermal characteristics characteristics symbol value unit thermal resistance C 64-pin quad ?at package q ja 50 ?c/w C plastic 56 pin shrink dil package q ja 50 ?c/w C plastic 52 pin plcc package q ja 50 ?c/w figure g-10 equivalent test load t j t a p d q ja ( ) + = p d k t j 273 + --------------------- = k p d t a 273 + ( ) q ja p d 2 + = v dd = 4.5/3.0 v r2 r1 c test point voltage pins r1 r2 c 4.5 v pa0C7, pb0C7, pc0C7 3.26k? 2.38k? 50pf 3.0 v pa0C7, pb0C7, pc0C7 10.91k? 6.32k? 50pf
mc68hc05b6 motorola g-21 mc68hc705b32 14 g.2.6 dc electrical characteristics table g-8 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.8 v dd C 0.8 v dd C 0.4 v dd C 0.4 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.1 0.4 0.4 1 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (extended) C 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd 6 1.5 2 1 10 20 60 60 tbd tbd tbd tbd tbd tbd tbd tbd ma ma ma ma a a a a eprom absolute maximum voltage programming voltage programming current read voltage v pp6 max v pp6 i pp6 v pp6r v dd 14.5 v dd 15.5 50 v dd 18 16 64 v dd 10% v v ma v high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current port b and port c pull-down (v in = v ih ) i rpd 80 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 5 a
motorola g-22 mc68hc05b6 mc68hc705b32 14 (1) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an e xternal square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all por ts con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. capacitance por ts (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c out c in c in 12 22 12 8 pf pf pf pf table g-8 dc electrical characteristics for 5v operation (continued) (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit
mc68hc05b6 motorola g-23 mc68hc705b32 14 (1) all i dd measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an e xternal square-wave clock source (f osc = 2.1mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all por ts con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. table g-9 dc electrical characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.3 v dd C 0.3 v dd C 0.1 v dd C 0.1 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.1 0.2 0.4 0.6 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (extended) C 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd 3 1 1.5 0.5 10 10 40 40 tbd tbd tbd tbd tbd tbd tbd tbd ma ma ma ma a a a a high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 0.2 1 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 0.2 1 a input current (C 40 to 125) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 5 a capacitance por ts (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c out c in c in 12 22 12 8 pf pf pf pf
motorola g-24 mc68hc05b6 mc68hc705b32 14 g.2.7 a/d converter characteristics g.2.8 control timing (1) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table g-10 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 1 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (1) 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (2) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
mc68hc05b6 motorola g-25 mc68hc705b32 14 (1) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table g-11 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 1 lsb quantization error uncertainty due to converter resolution 1 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors 2 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion internal rc oscillator 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling internal rc oscillator (1) 12 s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (2) input leakage on a/d pins pd0/an0Cpd7/an7, vrl, vrh 1 a
motorola g-26 mc68hc05b6 mc68hc705b32 14 (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table g-12 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 2.1 2.1 mhz mhz cycle time (see figure 9-1) t cyc 480 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eprom programming time t prog 5 15 ms eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t era t era t era t era 10 10 10 10 ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t prog t prog t prog t prog 10 10 15 20 ms ms ms ms timer (see figure g-11) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 125 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 90 ns
mc68hc05b6 motorola g-27 mc68hc705b32 14 (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . table g-13 control timing for operation at 3.3v (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 1.0 1.0 mhz mhz cycle time (see figure 9-1) t cyc 1000 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) C 40 to 105 (industrial) C 40 to 125 (automotive) t era t era t era t era 30 30 30 30 ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) C 40 to 85 (industrial) C 40 to 125 (automotive) t prog t prog t prog t prog 30 30 30 30 ms ms ms ms timer (see figure g-11) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 250 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 100 ns
motorola g-28 mc68hc05b6 mc68hc705b32 14 figure g-11 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
mc68hc05b6 motorola h-1 high speed operation 15 h high speed operation this section contains the electr ical speci?cations and associated timing inf or mation f or high speed versions of the mc68hc05b6 and mc68hc05b8 (f osc max = 8 mhz). the ordering information for these devices is contained in table h-1. note: the high speed version has the same device title as the standard version. high speed oper ation is selected via a chec k-bo x on the order f or m and will be con?r med on the listing veri?cation form. table h-1 ordering information device title package suf?x 0 to 70?c suf?x -40 to +85?c mc68hc05b6 52-pin plcc fn cfn 64-pin qfp fu cfu 56-pin sdip b cb mc68hc05b8 52-pin plcc fn cfn 64-pin qfp fu cfu 56-pin sdip b cb
motorola h-2 mc68hc05b6 high speed operation 15 h.1 dc electrical characteristics (1) all i dd measurements taken with suitab le decoupling capacitors across the po w er supply to suppress the tr ansient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25?c only . (3) run and wait i dd : measured using an external square-wave clock source (f osc = 8.0mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports con?gured as inputs; v il = 0.2 v and v ih = v dd C 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. table h-2 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = C 10 a i load = +10 a v oh v ol v dd C 0.1 0.1 v output high voltage (i load = 0.8 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2 output high voltage (i load = 1.6 ma) tdo, sclk, plma, plmb v oh v oh v dd C 0.8 v dd C 0.8 v output low voltage (i load = 1.6 ma) pa0C7, pb0C7, pc0C7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6 ma) reset v ol v ol 0.4 1 v input high voltage pa0C7, pb0C7, pc0C7, pd0C7, osc1, irq, reset, tcap1, tcap2, rdi v ih 0.7v dd v dd v input low voltage pa0C7, pb0C7, pc0C7, osc1, irq , reset, tcap1, tcap2, rdi v il v ss 0.2v dd v supply current (3) run (sm = 0) (see figure 11-2) run (sm = 1) (see figure 11-3) wait (sm = 0) (see figure 11-4) wait (sm = 1) (see figure 11-5) stop 0 to 70 (standard) C 40 to 85 (extended) i dd 12 3 4 2 10 20 ma ma ma ma a a high-z leakage current pa0C7, pb0C7, pc0C7, tdo, reset, sclk i il 1 a input current (0 to 70) irq, osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in 5 1 a capacitance ports (as input or output), reset, tdo, sclk irq, tcap1, tcap2, osc1, rdi pd0/an0Cpd7/an7 (a/d off) pd0/an0Cpd7/an7 (a/d on) c out c in c in c in 12 22 12 8 tbd tbd pf pf pf pf
mc68hc05b6 motorola h-3 high speed operation 15 h.2 a/d converter characteristics (1) performance veri?ed down to 2.5v ?vr, b ut accuracy is tested and guaranteed at ?vr = 5v10%. (2) source impedances greater than 10k? will adv ersely affect internal charging time during input sampling. (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2). table h-3 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 bit non-linearity max de viation from the best str aight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) 0.5 lsb quantization error uncertainty due to converter resolution 0.5 lsb absolute accuracy difference betw een the actual input v oltage and the full-scale equivalent of the binary code output code for all errors 1 lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss C 0.1 v rh v ?v r (1) minimum difference between v rh and v rl 3 v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 hex full scale reading conversion result when v in = v rh ff hex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0Cpd7/an7 12 pf input leakage (3) input leakage on a/d pins pd0/an0Cpd7/an7 vrl, vrh 1 1 a a
motorola h-4 mc68hc05b6 high speed operation 15 h.3 control timing for 5v operation (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc dc 8.0 8.0 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op dc 4.0 4.0 mhz mhz cycle time (see figure 9-1) t cyc 250 ns crystal oscillator start-up time (see figure 9-1) t oxov 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset input pulse width t rl 1.5 t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 t cyc t cyc watchdog reset output pulse width t dogl 1.5 t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) C 40 to 85 (extended) t era t era 10 10 ms ms eeprom byte program time (1) 0 to 70 (standard) C 40 to 85 (extended) t prog t prog 10 10 ms ms timer (see figure h-1) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 125 (3) t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ns interrupt pulse period t ilil (4) t cyc osc1 pulse width t oh , t ol 90 ns figure h-1 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information appendices high speed operation
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information appendices high speed operation
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